1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek MT65xx Pin Controller Device Tree Bindings
8
9maintainers:
10  - Sean Wang <sean.wang@kernel.org>
11
12description: |+
13  The Mediatek's Pin controller is used to control SoC pins.
14
15properties:
16  compatible:
17    enum:
18      - mediatek,mt2701-pinctrl
19      - mediatek,mt2712-pinctrl
20      - mediatek,mt6397-pinctrl
21      - mediatek,mt7623-pinctrl
22      - mediatek,mt8127-pinctrl
23      - mediatek,mt8135-pinctrl
24      - mediatek,mt8167-pinctrl
25      - mediatek,mt8173-pinctrl
26      - mediatek,mt8516-pinctrl
27
28  reg:
29    maxItems: 1
30
31  pins-are-numbered:
32    $ref: /schemas/types.yaml#/definitions/flag
33    description: |
34      Specify the subnodes are using numbered pinmux to specify pins.
35
36  gpio-controller: true
37
38  "#gpio-cells":
39    const: 2
40    description: |
41      Number of cells in GPIO specifier. Since the generic GPIO
42      binding is used, the amount of cells must be specified as 2. See the below
43      mentioned gpio binding representation for description of particular cells.
44
45  mediatek,pctl-regmap:
46    $ref: /schemas/types.yaml#/definitions/phandle-array
47    minItems: 1
48    maxItems: 2
49    description: |
50      Should be phandles of the syscfg node.
51
52  interrupt-controller: true
53
54  interrupts:
55    minItems: 1
56    maxItems: 3
57
58  "#interrupt-cells":
59    const: 2
60
61required:
62  - compatible
63  - pins-are-numbered
64  - gpio-controller
65  - "#gpio-cells"
66
67allOf:
68  - $ref: "pinctrl.yaml#"
69
70patternProperties:
71  '-[0-9]+$':
72    type: object
73    additionalProperties: false
74    patternProperties:
75      'pins':
76        type: object
77        additionalProperties: false
78        description: |
79          A pinctrl node should contain at least one subnodes representing the
80          pinctrl groups available on the machine. Each subnode will list the
81          pins it needs, and how they should be configured, with regard to muxer
82          configuration, pullups, drive strength, input enable/disable and input
83          schmitt.
84        $ref: "/schemas/pinctrl/pincfg-node.yaml"
85
86        properties:
87          pinmux:
88            description:
89              integer array, represents gpio pin number and mux setting.
90              Supported pin number and mux varies for different SoCs, and are
91              defined as macros in <soc>-pinfunc.h directly.
92
93          bias-disable: true
94
95          bias-pull-up:
96            description: |
97              Besides generic pinconfig options, it can be used as the pull up
98              settings for 2 pull resistors, R0 and R1. User can configure those
99              special pins. Some macros have been defined for this usage, such
100              as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for
101              valid arguments.
102
103          bias-pull-down: true
104
105          input-enable: true
106
107          input-disable: true
108
109          output-low: true
110
111          output-high: true
112
113          input-schmitt-enable: true
114
115          input-schmitt-disable: true
116
117          drive-strength:
118            description: |
119              Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA,
120              etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments.
121
122        required:
123          - pinmux
124
125additionalProperties: false
126
127examples:
128  - |
129    #include <dt-bindings/interrupt-controller/irq.h>
130    #include <dt-bindings/interrupt-controller/arm-gic.h>
131    #include <dt-bindings/pinctrl/mt8135-pinfunc.h>
132
133    soc {
134        #address-cells = <2>;
135        #size-cells = <2>;
136
137        syscfg_pctl_a: syscfg-pctl-a@10005000 {
138          compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
139          reg = <0 0x10005000 0 0x1000>;
140        };
141
142        syscfg_pctl_b: syscfg-pctl-b@1020c020 {
143          compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
144          reg = <0 0x1020C020 0 0x1000>;
145        };
146
147        pinctrl@1c20800 {
148          compatible = "mediatek,mt8135-pinctrl";
149          reg = <0 0x1000B000 0 0x1000>;
150          mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
151          pins-are-numbered;
152          gpio-controller;
153          #gpio-cells = <2>;
154          interrupt-controller;
155          #interrupt-cells = <2>;
156          interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
157              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
158              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
159
160          i2c0_pins_a: i2c0-0 {
161            pins1 {
162              pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
163                <MT8135_PIN_101_SCL0__FUNC_SCL0>;
164              bias-disable;
165            };
166          };
167
168          i2c1_pins_a: i2c1-0 {
169            pins {
170              pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
171                <MT8135_PIN_196_SCL1__FUNC_SCL1>;
172              bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
173            };
174          };
175
176          i2c2_pins_a: i2c2-0 {
177            pins1 {
178              pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
179              bias-pull-down;
180            };
181
182            pins2 {
183              pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
184              bias-pull-up;
185            };
186          };
187
188          i2c3_pins_a: i2c3-0 {
189            pins1 {
190              pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
191                <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
192              bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
193            };
194
195            pins2 {
196              pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
197                <MT8135_PIN_36_SDA3__FUNC_SDA3>;
198              output-low;
199              bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
200            };
201
202            pins3 {
203              pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
204                <MT8135_PIN_60_JTDI__FUNC_JTDI>;
205              drive-strength = <32>;
206            };
207          };
208        };
209    };
210