1* Marvell Dove SoC pinctrl driver for mpp 2 3Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding 4part and usage. 5 6Required properties: 7- compatible: "marvell,dove-pinctrl" 8- clocks: (optional) phandle of pdma clock 9 10Available mpp pins/groups and functions: 11Note: brackets (x) are not part of the mpp name for marvell,function and given 12only for more detailed description in this document. 13Note: pmu* also allows for Power Management functions listed below 14 15name pins functions 16================================================================================ 17mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu* 18mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu* 19mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt), 20 uart1(rts), pmu* 21mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act), 22 uart1(cts), lcd-spi(cs1), pmu* 23mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu* 24mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu* 25mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu* 26mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu* 27mpp8 8 gpio, pmu, watchdog(rstout), pmu* 28mpp9 9 gpio, pmu, pex1(clkreq), pmu* 29mpp10 10 gpio, pmu, ssp(sclk), pmu* 30mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl), 31 sdio1(ledctrl), pex0(clkreq), pmu* 32mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), 33 sata(act), pmu* 34mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp), 35 ssp(extclk), pmu* 36mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu* 37mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu* 38mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1) 39mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda), 40 ac97-1(sysclko) 41mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm) 42mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck) 43mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso), 44 ac97(sysclko) 45mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0), 46 uart1(cts), ssp(sfrm) 47mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi), 48 lcd-spi(mosi), uart1(cts), ssp(txd) 49mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck), 50 lcd-spi(sck), ssp(sclk) 51mpp_camera 24-39 gpio, camera 52mpp_sdio0 40-45 gpio, sdio0 53mpp_sdio1 46-51 gpio, sdio1 54mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp, 55 ssp/twsi 56mpp_spi0 58-61 gpio, spi0 57mpp_uart1 62-63 gpio, uart1 58mpp_nand 64-71 gpo, nand 59audio0 - i2s, ac97 60twsi - none, opt1, opt2, opt3 61 62Power Management functions (pmu*): 63pmu-nc Pin not driven by any PM function 64pmu-low Pin driven low (0) 65pmu-high Pin driven high (1) 66pmic(sdi) Pin is used for PMIC SDI 67cpu-pwr-down Pin is used for CPU_PWRDWN 68standby-pwr-down Pin is used for STBY_PWRDWN 69core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only) 70cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only) 71bat-fault Pin is used for BATTERY_FAULT 72ext0-wakeup Pin is used for EXT0_WU 73ext1-wakeup Pin is used for EXT0_WU 74ext2-wakeup Pin is used for EXT0_WU 75pmu-blink Pin is used for blink function 76 77Notes: 78* group "mpp_audio1" allows the following functions and gpio pins: 79 - gpio : gpio on pins 52-57 80 - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios 81 - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57 82 - spdifo : spdifo on pin 57, gpio on pins 52-55 83 - twsi : twsi on pins 56,57, gpio on pins 52-55 84 - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios 85 - ssp : ssp on pins 52-55, gpio on pins 56,57 86 - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios 87* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated 88 audio0 pins. 89* group "twsi" internally muxes twsi controller to the dedicated or option pins. 90