1* Marvell Armada 37xx SoC pin and gpio controller
2
3Each Armada 37xx SoC come with two pin and gpio controller one for the
4south bridge and the other for the north bridge.
5
6Inside this set of register the gpio latch allows exposing some
7configuration of the SoC and especially the clock frequency of the
8xtal. Hence, this node is a represent as syscon allowing sharing the
9register between multiple hardware block.
10
11GPIO and pin controller:
12------------------------
13
14Main node:
15
16Refer to pinctrl-bindings.txt in this directory for details of the
17common pinctrl bindings used by client devices, including the meaning
18of the phrase "pin configuration node".
19
20Required properties for pinctrl driver:
21
22- compatible:	"marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
23		for the south bridge
24		"marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
25		for the north bridge
26- reg: The first set of register are for pinctrl/gpio and the second
27  set for the interrupt controller
28- interrupts: list of the interrupt use by the gpio
29
30Available groups and functions for the North bridge:
31
32group: jtag
33 - pins 20-24
34 - functions jtag, gpio
35
36group sdio0
37 - pins 8-10
38 - functions sdio, gpio
39
40group emmc_nb
41 - pins 27-35
42 - functions emmc, gpio
43
44group pwm0
45 - pin 11 (GPIO1-11)
46 - functions pwm, gpio
47
48group pwm1
49 - pin 12
50 - functions pwm, gpio
51
52group pwm2
53 - pin 13
54 - functions pwm, gpio
55
56group pwm3
57 - pin 14
58 - functions pwm, gpio
59
60group pmic1
61 - pin 17
62 - functions pmic, gpio
63
64group pmic0
65 - pin 16
66 - functions pmic, gpio
67
68group i2c2
69 - pins 2-3
70 - functions i2c, gpio
71
72group i2c1
73 - pins 0-1
74 - functions i2c, gpio
75
76group spi_cs1
77 - pin 17
78 - functions spi, gpio
79
80group spi_cs2
81 - pin 18
82 - functions spi, gpio
83
84group spi_cs3
85 - pin 19
86 - functions spi, gpio
87
88group onewire
89 - pin 4
90 - functions onewire, gpio
91
92group uart1
93 - pins 25-26
94 - functions uart, gpio
95
96group spi_quad
97 - pins 15-16
98 - functions spi, gpio
99
100group uart2
101 - pins 9-10 and 18-19
102 - functions uart, gpio
103
104Available groups and functions for the South bridge:
105
106group usb32_drvvbus0
107 - pin 36
108 - functions drvbus, gpio
109
110group usb2_drvvbus1
111 - pin 37
112 - functions drvbus, gpio
113
114group sdio_sb
115 - pins 60-64
116 - functions sdio, gpio
117
118group rgmii
119 - pins 42-55
120 - functions mii, gpio
121
122group pcie1
123 - pins 39-40
124 - functions pcie, gpio
125
126group ptp
127 - pins 56-58
128 - functions ptp, gpio
129
130group ptp_clk
131 - pin 57
132 - functions ptp, mii
133
134group ptp_trig
135 - pin 58
136 - functions ptp, mii
137
138group mii_col
139 - pin 59
140 - functions mii, mii_err
141
142GPIO subnode:
143
144Please refer to gpio.txt in this directory for details of gpio-ranges property
145and the common GPIO bindings used by client devices.
146
147Required properties for gpio driver under the gpio subnode:
148- interrupts: List of interrupt specifier for the controllers interrupt.
149- gpio-controller: Marks the device node as a gpio controller.
150- #gpio-cells: Should be 2. The first cell is the GPIO number and the
151   second cell specifies GPIO flags, as defined in
152   <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and
153   GPIO_ACTIVE_LOW flags are supported.
154- gpio-ranges: Range of pins managed by the GPIO controller.
155
156Xtal Clock bindings for Marvell Armada 37xx SoCs
157------------------------------------------------
158
159see Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt
160
161
162Example:
163pinctrl_sb: pinctrl-sb@18800 {
164	compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd";
165	reg = <0x18800 0x100>, <0x18C00 0x20>;
166	gpio {
167		#gpio-cells = <2>;
168		gpio-ranges = <&pinctrl_sb 0 0 29>;
169		gpio-controller;
170		interrupts =
171		<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
172		<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
173		<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
174		<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
175		<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
176	};
177
178	rgmii_pins: mii-pins {
179		groups = "rgmii";
180		function = "mii";
181	};
182
183};
184