1f13980e4SGregory CLEMENT* Marvell Armada 37xx SoC pin and gpio controller 2f13980e4SGregory CLEMENT 3f13980e4SGregory CLEMENTEach Armada 37xx SoC come with two pin and gpio controller one for the 4f13980e4SGregory CLEMENTsouth bridge and the other for the north bridge. 5f13980e4SGregory CLEMENT 6f13980e4SGregory CLEMENTInside this set of register the gpio latch allows exposing some 7f13980e4SGregory CLEMENTconfiguration of the SoC and especially the clock frequency of the 8f13980e4SGregory CLEMENTxtal. Hence, this node is a represent as syscon allowing sharing the 9f13980e4SGregory CLEMENTregister between multiple hardware block. 10f13980e4SGregory CLEMENT 11f13980e4SGregory CLEMENTGPIO and pin controller: 12f13980e4SGregory CLEMENT------------------------ 13f13980e4SGregory CLEMENT 14f13980e4SGregory CLEMENTMain node: 15f13980e4SGregory CLEMENT 16f13980e4SGregory CLEMENTRefer to pinctrl-bindings.txt in this directory for details of the 17f13980e4SGregory CLEMENTcommon pinctrl bindings used by client devices, including the meaning 18f13980e4SGregory CLEMENTof the phrase "pin configuration node". 19f13980e4SGregory CLEMENT 20f13980e4SGregory CLEMENTRequired properties for pinctrl driver: 21f13980e4SGregory CLEMENT 22f13980e4SGregory CLEMENT- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd" 23f13980e4SGregory CLEMENT for the south bridge 24f13980e4SGregory CLEMENT "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd" 25f13980e4SGregory CLEMENT for the north bridge 26f13980e4SGregory CLEMENT- reg: The first set of register are for pinctrl/gpio and the second 27f13980e4SGregory CLEMENT set for the interrupt controller 28f13980e4SGregory CLEMENT- interrupts: list of the interrupt use by the gpio 29f13980e4SGregory CLEMENT 30f13980e4SGregory CLEMENTAvailable groups and functions for the North bridge: 31f13980e4SGregory CLEMENT 32f13980e4SGregory CLEMENTgroup: jtag 33f13980e4SGregory CLEMENT - pins 20-24 34f13980e4SGregory CLEMENT - functions jtag, gpio 35f13980e4SGregory CLEMENT 36f13980e4SGregory CLEMENTgroup sdio0 37f13980e4SGregory CLEMENT - pins 8-10 38f13980e4SGregory CLEMENT - functions sdio, gpio 39f13980e4SGregory CLEMENT 40f13980e4SGregory CLEMENTgroup emmc_nb 41f13980e4SGregory CLEMENT - pins 27-35 42f13980e4SGregory CLEMENT - functions emmc, gpio 43f13980e4SGregory CLEMENT 44f13980e4SGregory CLEMENTgroup pwm0 45f13980e4SGregory CLEMENT - pin 11 (GPIO1-11) 46f13980e4SGregory CLEMENT - functions pwm, gpio 47f13980e4SGregory CLEMENT 48f13980e4SGregory CLEMENTgroup pwm1 49f13980e4SGregory CLEMENT - pin 12 50f13980e4SGregory CLEMENT - functions pwm, gpio 51f13980e4SGregory CLEMENT 52f13980e4SGregory CLEMENTgroup pwm2 53f13980e4SGregory CLEMENT - pin 13 54f13980e4SGregory CLEMENT - functions pwm, gpio 55f13980e4SGregory CLEMENT 56f13980e4SGregory CLEMENTgroup pwm3 57f13980e4SGregory CLEMENT - pin 14 58f13980e4SGregory CLEMENT - functions pwm, gpio 59f13980e4SGregory CLEMENT 60f13980e4SGregory CLEMENTgroup pmic1 61823868fcSMarek Behún - pin 7 62f13980e4SGregory CLEMENT - functions pmic, gpio 63f13980e4SGregory CLEMENT 64f13980e4SGregory CLEMENTgroup pmic0 65823868fcSMarek Behún - pin 6 66f13980e4SGregory CLEMENT - functions pmic, gpio 67f13980e4SGregory CLEMENT 68f13980e4SGregory CLEMENTgroup i2c2 69f13980e4SGregory CLEMENT - pins 2-3 70f13980e4SGregory CLEMENT - functions i2c, gpio 71f13980e4SGregory CLEMENT 72f13980e4SGregory CLEMENTgroup i2c1 73f13980e4SGregory CLEMENT - pins 0-1 74f13980e4SGregory CLEMENT - functions i2c, gpio 75f13980e4SGregory CLEMENT 76f13980e4SGregory CLEMENTgroup spi_cs1 77f13980e4SGregory CLEMENT - pin 17 78f13980e4SGregory CLEMENT - functions spi, gpio 79f13980e4SGregory CLEMENT 80f13980e4SGregory CLEMENTgroup spi_cs2 81f13980e4SGregory CLEMENT - pin 18 82f13980e4SGregory CLEMENT - functions spi, gpio 83f13980e4SGregory CLEMENT 84f13980e4SGregory CLEMENTgroup spi_cs3 85f13980e4SGregory CLEMENT - pin 19 86f13980e4SGregory CLEMENT - functions spi, gpio 87f13980e4SGregory CLEMENT 88f13980e4SGregory CLEMENTgroup onewire 89f13980e4SGregory CLEMENT - pin 4 90f13980e4SGregory CLEMENT - functions onewire, gpio 91f13980e4SGregory CLEMENT 92f13980e4SGregory CLEMENTgroup uart1 93f13980e4SGregory CLEMENT - pins 25-26 94f13980e4SGregory CLEMENT - functions uart, gpio 95f13980e4SGregory CLEMENT 96f13980e4SGregory CLEMENTgroup spi_quad 97f13980e4SGregory CLEMENT - pins 15-16 98f13980e4SGregory CLEMENT - functions spi, gpio 99f13980e4SGregory CLEMENT 100fbe87498SMiquel Raynalgroup uart2 101fbe87498SMiquel Raynal - pins 9-10 and 18-19 102f13980e4SGregory CLEMENT - functions uart, gpio 103f13980e4SGregory CLEMENT 104f13980e4SGregory CLEMENTAvailable groups and functions for the South bridge: 105f13980e4SGregory CLEMENT 106f13980e4SGregory CLEMENTgroup usb32_drvvbus0 107f13980e4SGregory CLEMENT - pin 36 108f13980e4SGregory CLEMENT - functions drvbus, gpio 109f13980e4SGregory CLEMENT 110f13980e4SGregory CLEMENTgroup usb2_drvvbus1 111f13980e4SGregory CLEMENT - pin 37 112f13980e4SGregory CLEMENT - functions drvbus, gpio 113f13980e4SGregory CLEMENT 114f13980e4SGregory CLEMENTgroup sdio_sb 115823868fcSMarek Behún - pins 60-65 116f13980e4SGregory CLEMENT - functions sdio, gpio 117f13980e4SGregory CLEMENT 118f13980e4SGregory CLEMENTgroup rgmii 119823868fcSMarek Behún - pins 42-53 120f13980e4SGregory CLEMENT - functions mii, gpio 121f13980e4SGregory CLEMENT 122f13980e4SGregory CLEMENTgroup pcie1 123823868fcSMarek Behún - pins 39 124f13980e4SGregory CLEMENT - functions pcie, gpio 125f13980e4SGregory CLEMENT 126823868fcSMarek Behúngroup pcie1_clkreq 127823868fcSMarek Behún - pins 40 128823868fcSMarek Behún - functions pcie, gpio 129823868fcSMarek Behún 1303fbb9a8dSGregory CLEMENTgroup pcie1_wakeup 1313fbb9a8dSGregory CLEMENT - pins 41 1323fbb9a8dSGregory CLEMENT - functions pcie, gpio 1333fbb9a8dSGregory CLEMENT 134823868fcSMarek Behúngroup smi 135823868fcSMarek Behún - pins 54-55 136823868fcSMarek Behún - functions smi, gpio 137823868fcSMarek Behún 138f13980e4SGregory CLEMENTgroup ptp 1393fbb9a8dSGregory CLEMENT - pins 56 140f13980e4SGregory CLEMENT - functions ptp, gpio 141f13980e4SGregory CLEMENT 142f13980e4SGregory CLEMENTgroup ptp_clk 143f13980e4SGregory CLEMENT - pin 57 144f13980e4SGregory CLEMENT - functions ptp, mii 145f13980e4SGregory CLEMENT 146f13980e4SGregory CLEMENTgroup ptp_trig 147f13980e4SGregory CLEMENT - pin 58 148f13980e4SGregory CLEMENT - functions ptp, mii 149f13980e4SGregory CLEMENT 150f13980e4SGregory CLEMENTgroup mii_col 151f13980e4SGregory CLEMENT - pin 59 152f13980e4SGregory CLEMENT - functions mii, mii_err 153f13980e4SGregory CLEMENT 154f13980e4SGregory CLEMENTGPIO subnode: 155f13980e4SGregory CLEMENT 156f13980e4SGregory CLEMENTPlease refer to gpio.txt in this directory for details of gpio-ranges property 157f13980e4SGregory CLEMENTand the common GPIO bindings used by client devices. 158f13980e4SGregory CLEMENT 159f13980e4SGregory CLEMENTRequired properties for gpio driver under the gpio subnode: 160f13980e4SGregory CLEMENT- interrupts: List of interrupt specifier for the controllers interrupt. 161f13980e4SGregory CLEMENT- gpio-controller: Marks the device node as a gpio controller. 162f13980e4SGregory CLEMENT- #gpio-cells: Should be 2. The first cell is the GPIO number and the 163f13980e4SGregory CLEMENT second cell specifies GPIO flags, as defined in 164f13980e4SGregory CLEMENT <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and 165f13980e4SGregory CLEMENT GPIO_ACTIVE_LOW flags are supported. 166f13980e4SGregory CLEMENT- gpio-ranges: Range of pins managed by the GPIO controller. 167f13980e4SGregory CLEMENT 168f13980e4SGregory CLEMENTXtal Clock bindings for Marvell Armada 37xx SoCs 169f13980e4SGregory CLEMENT------------------------------------------------ 170f13980e4SGregory CLEMENT 171f13980e4SGregory CLEMENTsee Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt 172f13980e4SGregory CLEMENT 173f13980e4SGregory CLEMENT 174f13980e4SGregory CLEMENTExample: 175f13980e4SGregory CLEMENTpinctrl_sb: pinctrl-sb@18800 { 176f13980e4SGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; 177f13980e4SGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 178f13980e4SGregory CLEMENT gpio { 179f13980e4SGregory CLEMENT #gpio-cells = <2>; 180f13980e4SGregory CLEMENT gpio-ranges = <&pinctrl_sb 0 0 29>; 181f13980e4SGregory CLEMENT gpio-controller; 182f13980e4SGregory CLEMENT interrupts = 183f13980e4SGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 184f13980e4SGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 185f13980e4SGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 186f13980e4SGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 187f13980e4SGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 188f13980e4SGregory CLEMENT }; 189f13980e4SGregory CLEMENT 190f13980e4SGregory CLEMENT rgmii_pins: mii-pins { 191f13980e4SGregory CLEMENT groups = "rgmii"; 192f13980e4SGregory CLEMENT function = "mii"; 193f13980e4SGregory CLEMENT }; 194f13980e4SGregory CLEMENT 195f13980e4SGregory CLEMENT}; 196