1*d2083893SLakshmi Sowjanya D# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*d2083893SLakshmi Sowjanya D%YAML 1.2 3*d2083893SLakshmi Sowjanya D--- 4*d2083893SLakshmi Sowjanya D$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml# 5*d2083893SLakshmi Sowjanya D$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d2083893SLakshmi Sowjanya D 7*d2083893SLakshmi Sowjanya Dtitle: Intel Keem Bay pin controller Device Tree Bindings 8*d2083893SLakshmi Sowjanya D 9*d2083893SLakshmi Sowjanya Dmaintainers: 10*d2083893SLakshmi Sowjanya D - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> 11*d2083893SLakshmi Sowjanya D 12*d2083893SLakshmi Sowjanya Ddescription: | 13*d2083893SLakshmi Sowjanya D Intel Keem Bay SoC integrates a pin controller which enables control 14*d2083893SLakshmi Sowjanya D of pin directions, input/output values and configuration 15*d2083893SLakshmi Sowjanya D for a total of 80 pins. 16*d2083893SLakshmi Sowjanya D 17*d2083893SLakshmi Sowjanya Dproperties: 18*d2083893SLakshmi Sowjanya D compatible: 19*d2083893SLakshmi Sowjanya D const: intel,keembay-pinctrl 20*d2083893SLakshmi Sowjanya D 21*d2083893SLakshmi Sowjanya D reg: 22*d2083893SLakshmi Sowjanya D maxItems: 2 23*d2083893SLakshmi Sowjanya D 24*d2083893SLakshmi Sowjanya D gpio-controller: true 25*d2083893SLakshmi Sowjanya D 26*d2083893SLakshmi Sowjanya D '#gpio-cells': 27*d2083893SLakshmi Sowjanya D const: 2 28*d2083893SLakshmi Sowjanya D 29*d2083893SLakshmi Sowjanya D ngpios: 30*d2083893SLakshmi Sowjanya D description: The number of GPIOs exposed. 31*d2083893SLakshmi Sowjanya D const: 80 32*d2083893SLakshmi Sowjanya D 33*d2083893SLakshmi Sowjanya D interrupts: 34*d2083893SLakshmi Sowjanya D description: 35*d2083893SLakshmi Sowjanya D Specifies the interrupt lines to be used by the controller. 36*d2083893SLakshmi Sowjanya D Each interrupt line is shared by upto 4 GPIO lines. 37*d2083893SLakshmi Sowjanya D maxItems: 8 38*d2083893SLakshmi Sowjanya D 39*d2083893SLakshmi Sowjanya D interrupt-controller: true 40*d2083893SLakshmi Sowjanya D 41*d2083893SLakshmi Sowjanya D '#interrupt-cells': 42*d2083893SLakshmi Sowjanya D const: 2 43*d2083893SLakshmi Sowjanya D 44*d2083893SLakshmi Sowjanya DpatternProperties: 45*d2083893SLakshmi Sowjanya D '^gpio@[0-9a-f]*$': 46*d2083893SLakshmi Sowjanya D type: object 47*d2083893SLakshmi Sowjanya D 48*d2083893SLakshmi Sowjanya D description: 49*d2083893SLakshmi Sowjanya D Child nodes can be specified to contain pin configuration information, 50*d2083893SLakshmi Sowjanya D which can then be utilized by pinctrl client devices. 51*d2083893SLakshmi Sowjanya D The following properties are supported. 52*d2083893SLakshmi Sowjanya D 53*d2083893SLakshmi Sowjanya D properties: 54*d2083893SLakshmi Sowjanya D pins: 55*d2083893SLakshmi Sowjanya D description: | 56*d2083893SLakshmi Sowjanya D The name(s) of the pins to be configured in the child node. 57*d2083893SLakshmi Sowjanya D Supported pin names are "GPIO0" up to "GPIO79". 58*d2083893SLakshmi Sowjanya D 59*d2083893SLakshmi Sowjanya D bias-disable: true 60*d2083893SLakshmi Sowjanya D 61*d2083893SLakshmi Sowjanya D bias-pull-down: true 62*d2083893SLakshmi Sowjanya D 63*d2083893SLakshmi Sowjanya D bias-pull-up: true 64*d2083893SLakshmi Sowjanya D 65*d2083893SLakshmi Sowjanya D drive-strength: 66*d2083893SLakshmi Sowjanya D description: IO pads drive strength in milli Ampere. 67*d2083893SLakshmi Sowjanya D enum: [2, 4, 8, 12] 68*d2083893SLakshmi Sowjanya D 69*d2083893SLakshmi Sowjanya D bias-bus-hold: 70*d2083893SLakshmi Sowjanya D type: boolean 71*d2083893SLakshmi Sowjanya D 72*d2083893SLakshmi Sowjanya D input-schmitt-enable: 73*d2083893SLakshmi Sowjanya D type: boolean 74*d2083893SLakshmi Sowjanya D 75*d2083893SLakshmi Sowjanya D slew-rate: 76*d2083893SLakshmi Sowjanya D description: GPIO slew rate control. 77*d2083893SLakshmi Sowjanya D 0 - Fast(~100MHz) 78*d2083893SLakshmi Sowjanya D 1 - Slow(~50MHz) 79*d2083893SLakshmi Sowjanya D enum: [0, 1] 80*d2083893SLakshmi Sowjanya D 81*d2083893SLakshmi Sowjanya DadditionalProperties: false 82*d2083893SLakshmi Sowjanya D 83*d2083893SLakshmi Sowjanya Drequired: 84*d2083893SLakshmi Sowjanya D - compatible 85*d2083893SLakshmi Sowjanya D - reg 86*d2083893SLakshmi Sowjanya D - gpio-controller 87*d2083893SLakshmi Sowjanya D - ngpios 88*d2083893SLakshmi Sowjanya D - '#gpio-cells' 89*d2083893SLakshmi Sowjanya D - interrupts 90*d2083893SLakshmi Sowjanya D - interrupt-controller 91*d2083893SLakshmi Sowjanya D - '#interrupt-cells' 92*d2083893SLakshmi Sowjanya D 93*d2083893SLakshmi Sowjanya Dexamples: 94*d2083893SLakshmi Sowjanya D - | 95*d2083893SLakshmi Sowjanya D #include <dt-bindings/interrupt-controller/arm-gic.h> 96*d2083893SLakshmi Sowjanya D #include <dt-bindings/interrupt-controller/irq.h> 97*d2083893SLakshmi Sowjanya D // Example 1 98*d2083893SLakshmi Sowjanya D gpio@0 { 99*d2083893SLakshmi Sowjanya D compatible = "intel,keembay-pinctrl"; 100*d2083893SLakshmi Sowjanya D reg = <0x600b0000 0x88>, 101*d2083893SLakshmi Sowjanya D <0x600b0190 0x1ac>; 102*d2083893SLakshmi Sowjanya D gpio-controller; 103*d2083893SLakshmi Sowjanya D ngpios = <0x50>; 104*d2083893SLakshmi Sowjanya D #gpio-cells = <0x2>; 105*d2083893SLakshmi Sowjanya D interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 106*d2083893SLakshmi Sowjanya D <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 107*d2083893SLakshmi Sowjanya D <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 108*d2083893SLakshmi Sowjanya D <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 109*d2083893SLakshmi Sowjanya D <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 110*d2083893SLakshmi Sowjanya D <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 111*d2083893SLakshmi Sowjanya D <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 112*d2083893SLakshmi Sowjanya D <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 113*d2083893SLakshmi Sowjanya D interrupt-controller; 114*d2083893SLakshmi Sowjanya D #interrupt-cells = <2>; 115*d2083893SLakshmi Sowjanya D }; 116*d2083893SLakshmi Sowjanya D 117*d2083893SLakshmi Sowjanya D // Example 2 118*d2083893SLakshmi Sowjanya D gpio@1 { 119*d2083893SLakshmi Sowjanya D compatible = "intel,keembay-pinctrl"; 120*d2083893SLakshmi Sowjanya D reg = <0x600c0000 0x88>, 121*d2083893SLakshmi Sowjanya D <0x600c0190 0x1ac>; 122*d2083893SLakshmi Sowjanya D gpio-controller; 123*d2083893SLakshmi Sowjanya D ngpios = <0x50>; 124*d2083893SLakshmi Sowjanya D #gpio-cells = <0x2>; 125*d2083893SLakshmi Sowjanya D interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 126*d2083893SLakshmi Sowjanya D <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 127*d2083893SLakshmi Sowjanya D <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 128*d2083893SLakshmi Sowjanya D <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 129*d2083893SLakshmi Sowjanya D <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 130*d2083893SLakshmi Sowjanya D <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 131*d2083893SLakshmi Sowjanya D <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 132*d2083893SLakshmi Sowjanya D <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 133*d2083893SLakshmi Sowjanya D interrupt-controller; 134*d2083893SLakshmi Sowjanya D #interrupt-cells = <2>; 135*d2083893SLakshmi Sowjanya D }; 136