1* Freescale i.MX7ULP IOMUX Controller
2
3i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
4ports and IOMUXC DDR for DDR interface.
5
6Note:
7This binding doc is only for the IOMUXC1 support in A7 Domain and it only
8supports generic pin config.
9
10Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
11binding.
12
13=== Pin Controller Node ===
14
15Required properties:
16- compatible:	"fsl,imx7ulp-iomuxc1"
17- reg:		Should contain the base physical address and size of the iomuxc
18		registers.
19
20=== Pin Configuration Node ===
21- pinmux: One integers array, represents a group of pins mux setting.
22	The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
23	a specific function.
24
25	NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
26	and config register as follows:
27	<mux_conf_reg input_reg mux_mode input_val>
28
29	Refer to imx7ulp-pinfunc.h in in device tree source folder for all
30	available imx7ulp PIN_FUNC_ID.
31
32Optional Properties:
33- drive-strength		Integer. Controls Drive Strength
34					0: Standard
35					1: Hi Driver
36- drive-push-pull		Bool. Enable Pin Push-pull
37- drive-open-drain		Bool. Enable Pin Open-drian
38- slew-rate:			Integer. Controls Slew Rate
39					0: Standard
40					1: Slow
41- bias-disable:			Bool. Pull disabled
42- bias-pull-down:		Bool. Pull down on pin
43- bias-pull-up:			Bool. Pull up on pin
44
45Examples:
46#include "imx7ulp-pinfunc.h"
47
48/* Pin Controller Node */
49iomuxc1: iomuxc@40ac0000 {
50	compatible = "fsl,imx7ulp-iomuxc1";
51	reg = <0x40ac0000 0x1000>;
52
53	/* Pin Configuration Node */
54	pinctrl_lpuart4: lpuart4grp {
55		pinmux = <
56			IMX7ULP_PAD_PTC3__LPUART4_RX
57			IMX7ULP_PAD_PTC2__LPUART4_TX
58		>;
59		bias-pull-up;
60	};
61};
62