1Axis ARTPEC-6 Pin Controller
2
3Required properties:
4- compatible: "axis,artpec6-pinctrl".
5- reg: Should contain the register physical address and length for the pin
6       controller.
7
8A pinctrl node should contain at least one subnode representing the pinctrl
9groups available on the machine. Each subnode will list the mux function
10required and what pin group it will use. Each subnode will also configure the
11drive strength and bias pullup of the pin group. If either of these options is
12not set, its actual value will be unspecified.
13
14
15Required subnode-properties:
16- function: Function to mux.
17- groups: Name of the pin group to use for the function above.
18
19	Available functions and groups (function: group0, group1...):
20		gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0,
21		      i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0,
22		      spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart1grp0,
23		      uart2grp0, uart2grp1, uart3grp0, uart4grp0, uart5grp0,
24		      uart5nocts
25		cpuclkout: cpuclkoutgrp0
26		udlclkout: udlclkoutgrp0
27		i2c1: i2c1grp0
28		i2c2: i2c2grp0
29		i2c3: i2c3grp0
30		i2s0: i2s0grp0
31		i2s1: i2s1grp0
32		i2srefclk: i2srefclkgrp0
33		spi0: spi0grp0
34		spi1: spi1grp0
35		pciedebug: pciedebuggrp0
36		uart0: uart0grp0, uart0grp1
37		uart1: uart1grp0
38		uart2: uart2grp0, uart2grp1
39		uart3: uart3grp0
40		uart4: uart4grp0
41		uart5: uart5grp0, uart5nocts
42		nand: nandgrp0
43		sdio0: sdio0grp0
44		sdio1: sdio1grp0
45		ethernet: ethernetgrp0
46
47
48Optional subnode-properties (see pinctrl-bindings.txt):
49- drive-strength: 4, 6, 8, 9 mA.  For SD and NAND pins, this is for 3.3V VCCQ3.
50- bias-pull-up
51- bias-disable
52
53Examples:
54pinctrl@f801d000 {
55	compatible = "axis,artpec6-pinctrl";
56	reg = <0xf801d000 0x400>;
57
58	pinctrl_uart0: uart0grp {
59		function = "uart0";
60		groups = "uart0grp0";
61		drive-strength = <4>;
62		bias-pull-up;
63	};
64	pinctrl_uart3: uart3grp {
65		function = "uart3";
66		groups = "uart3grp0";
67	};
68};
69uart0: uart@f8036000 {
70	compatible = "arm,pl011", "arm,primecell";
71	reg = <0xf8036000 0x1000>;
72	interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
73	clocks = <&pll2div24>, <&apb_pclk>;
74	clock-names = "uart_clk", "apb_pclk";
75	pinctrl-names = "default";
76	pinctrl-0 = <&pinctrl_uart0>;
77};
78uart3: uart@f8039000 {
79	compatible = "arm,pl011", "arm,primecell";
80	reg = <0xf8039000 0x1000>;
81	interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>;
82	clocks = <&pll2div24>, <&apb_pclk>;
83	clock-names = "uart_clk", "apb_pclk";
84	pinctrl-names = "default";
85	pinctrl-0 = <&pinctrl_uart3>;
86};
87