1# SPDX-License-Identifier: GPL-2.0-or-later
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ASPEED AST2500 Pin Controller
8
9maintainers:
10  - Andrew Jeffery <andrew@aj.id.au>
11
12description: |+
13  The pin controller node should be the child of a syscon node with the
14  required property:
15
16  - compatible: 	Should be one of the following:
17  			"aspeed,ast2500-scu", "syscon", "simple-mfd"
18  			"aspeed,g5-scu", "syscon", "simple-mfd"
19
20  Refer to the the bindings described in
21  Documentation/devicetree/bindings/mfd/syscon.yaml
22
23properties:
24  compatible:
25    const: aspeed,ast2500-pinctrl
26  reg:
27    description: |
28      A hint for the memory regions associated with the pin-controller
29  aspeed,external-nodes:
30    minItems: 2
31    maxItems: 2
32    allOf:
33      - $ref: /schemas/types.yaml#/definitions/phandle-array
34    description: |
35      A cell of phandles to external controller nodes:
36      0: compatible with "aspeed,ast2500-gfx", "syscon"
37      1: compatible with "aspeed,ast2500-lhc", "syscon"
38
39patternProperties:
40  '^.*$':
41    if:
42      type: object
43    then:
44      patternProperties:
45        "^function|groups$":
46          allOf:
47            - $ref: "/schemas/types.yaml#/definitions/string"
48            - enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14,
49              ADC15, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT,
50              DDCCLK, DDCDAT, ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4,
51              GPID6, GPIE0, GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13,
52              I2C14, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, LAD0, LAD1,
53              LAD2, LAD3, LCLK, LFRAME, LPCHC, LPCPD, LPCPLUS, LPCPME, LPCRST,
54              LPCSMI, LSIRQ, MAC1LINK, MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2,
55              NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3,
56              NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1,
57              NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0, PWM1, PWM2,
58              PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, RMII2, RXD1,
59              RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
60              SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1,
61              SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI,
62              SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1,
63              SPI1DEBUG, SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO,
64              SPI2MOSI, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1,
65              TXD2, TXD3, TXD4, UART6, USB11BHID, USB2AD, USB2AH, USB2BD,
66              USB2BH, USBCKI, VGABIOSROM, VGAHS, VGAVS, VPI24, VPO, WDTRST1,
67              WDTRST2, ]
68
69required:
70  - compatible
71  - aspeed,external-nodes
72
73examples:
74  - |
75    apb {
76        compatible = "simple-bus";
77        #address-cells = <1>;
78        #size-cells = <1>;
79        ranges;
80
81        syscon: scu@1e6e2000 {
82            compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
83            reg = <0x1e6e2000 0x1a8>;
84
85            pinctrl: pinctrl {
86                compatible = "aspeed,g5-pinctrl";
87                aspeed,external-nodes = <&gfx>, <&lhc>;
88
89                pinctrl_i2c3_default: i2c3_default {
90                    function = "I2C3";
91                    groups = "I2C3";
92                };
93
94                pinctrl_gpioh0_unbiased_default: gpioh0 {
95                    pins = "A18";
96                    bias-disable;
97                };
98            };
99        };
100
101        gfx: display@1e6e6000 {
102            compatible = "aspeed,ast2500-gfx", "syscon";
103            reg = <0x1e6e6000 0x1000>;
104        };
105    };
106
107    lpc: lpc@1e789000 {
108        compatible = "aspeed,ast2500-lpc", "simple-mfd";
109        reg = <0x1e789000 0x1000>;
110
111        #address-cells = <1>;
112        #size-cells = <1>;
113        ranges = <0x0 0x1e789000 0x1000>;
114
115        lpc_host: lpc-host@80 {
116            compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
117            reg = <0x80 0x1e0>;
118            reg-io-width = <4>;
119
120            #address-cells = <1>;
121            #size-cells = <1>;
122            ranges = <0x0 0x80 0x1e0>;
123
124            lhc: lhc@20 {
125                   compatible = "aspeed,ast2500-lhc";
126                   reg = <0x20 0x24 0x48 0x8>;
127            };
128        };
129    };
130