1Actions Semi S900 Pin Controller
2
3This binding describes the pin controller found in the S900 SoC.
4
5Required Properties:
6
7- compatible:   Should be "actions,s900-pinctrl"
8- reg:          Should contain the register base address and size of
9                the pin controller.
10- clocks:       phandle of the clock feeding the pin controller
11- gpio-controller: Marks the device node as a GPIO controller.
12- gpio-ranges: Specifies the mapping between gpio controller and
13               pin-controller pins.
14- #gpio-cells: Should be two. The first cell is the gpio pin number
15               and the second cell is used for optional parameters.
16- interrupt-controller: Marks the device node as an interrupt controller.
17- #interrupt-cells: Specifies the number of cells needed to encode an
18                    interrupt.  Shall be set to 2.  The first cell
19                    defines the interrupt number, the second encodes
20                    the trigger flags described in
21                    bindings/interrupt-controller/interrupts.txt
22- interrupts: The interrupt outputs from the controller. There is one GPIO
23              interrupt per GPIO bank. The number of interrupts listed depends
24              on the number of GPIO banks on the SoC. The interrupts must be
25              ordered by bank, starting with bank 0.
26
27Please refer to pinctrl-bindings.txt in this directory for details of the
28common pinctrl bindings used by client devices, including the meaning of the
29phrase "pin configuration node".
30
31The pin configuration nodes act as a container for an arbitrary number of
32subnodes. Each of these subnodes represents some desired configuration for a
33pin, a group, or a list of pins or groups. This configuration can include the
34mux function to select on those group(s), and various pin configuration
35parameters, such as pull-up, drive strength, etc.
36
37PIN CONFIGURATION NODES:
38
39The name of each subnode is not important; all subnodes should be enumerated
40and processed purely based on their content.
41
42Each subnode only affects those parameters that are explicitly listed. In
43other words, a subnode that lists a mux function but no pin configuration
44parameters implies no information about any pin configuration parameters.
45Similarly, a pin subnode that describes a pullup parameter implies no
46information about e.g. the mux function.
47
48Pinmux functions are available only for the pin groups while pinconf
49parameters are available for both pin groups and individual pins.
50
51The following generic properties as defined in pinctrl-bindings.txt are valid
52to specify in a pin configuration subnode:
53
54Required Properties:
55
56- pins:           An array of strings, each string containing the name of a pin.
57                  These pins are used for selecting the pull control and schmitt
58                  trigger parameters. The following are the list of pins
59                  available:
60
61                  eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv,
62                  eth_rxd1, eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio,
63                  sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, i2s_lrclk0,
64                  i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
65                  pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, eram_a5,
66                  eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11,
67                  lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
68                  lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan,
69                  lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
70                  lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean,
71                  sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,
72                  sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
73                  spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
74                  uart0_tx, uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb,
75                  uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, uart4_rx,
76                  uart4_tx, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata,
77                  i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, csi0_dn1,
78                  csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, csi0_dn3,
79                  csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp,
80                  dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk,
81                  csi1_dn0,csi1_dp0,csi1_dn1, csi1_dp1, csi1_cn, csi1_cp,
82                  sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3,
83                  nand0_d4, nand0_d5, nand0_d6, nand0_d7, nand0_dqs,
84                  nand0_dqsn, nand0_ale, nand0_cle, nand0_ceb0, nand0_ceb1,
85                  nand0_ceb2, nand0_ceb3, nand1_d0, nand1_d1, nand1_d2,
86                  nand1_d3, nand1_d4, nand1_d5, nand1_d6, nand1_d7, nand1_dqs,
87                  nand1_dqsn, nand1_ale, nand1_cle, nand1_ceb0, nand1_ceb1,
88                  nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, sgpio2, sgpio3
89
90- groups:         An array of strings, each string containing the name of a pin
91                  group. These pin groups are used for selecting the pinmux
92                  functions.
93
94                  lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp,
95                  sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp,
96                  rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp,
97                  rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp,
98                  i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp,
99                  pcm1_clk_mfp, pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp,
100                  eram_a7_mfp, eram_a8_mfp, eram_a9_mfp, eram_a10_mfp,
101                  eram_a11_mfp, lvds_oep_odn_mfp, lvds_ocp_obn_mfp,
102                  lvds_oap_oan_mfp, lvds_e_mfp, spi0_sclk_mosi_mfp, spi0_ss_mfp,
103                  spi0_miso_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
104                  uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
105                  sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_clk_mfp,
106                  uart0_rx_mfp, nand0_d0_ceb3_mfp, uart0_tx_mfp, i2c0_mfp,
107                  csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, csi1_dn0_cp_mfp,
108                  dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp,
109                  nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp,
110                  csi1_dn0_dp0_mfp, uart4_rx_tx_mfp
111
112
113                  These pin groups are used for selecting the drive strength
114                  parameters.
115
116                  sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv,
117                  rmii_tx_d0_d1_drv, rmii_txen_rxer_drv, rmii_crs_dv_drv,
118                  rmii_rx_d1_d0_drv, rmii_ref_clk_drv, rmii_mdc_mdio_drv,
119                  sirq_0_1_drv, sirq2_drv, i2s_d0_d1_drv, i2s_lr_m_clk0_drv,
120                  i2s_blk1_mclk1_drv, pcm1_in_out_drv, lvds_oap_oan_drv,
121                  lvds_oep_odn_drv, lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv,
122                  sd1_d3_d0_drv, sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv,
123                  spi0_ss_miso_drv, uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv,
124                  uart3_drv, i2c0_drv, i2c1_drv, i2c2_drv, sensor0_drv
125
126                  These pin groups are used for selecting the slew rate
127                  parameters.
128
129                  sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr,
130                  rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr,
131                  rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr,
132                  i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr,
133                  pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr,
134                  spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr,
135                  uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr,
136                  sensor0_sr
137
138- function:       An array of strings, each string containing the name of the
139                  pinmux functions. These functions can only be selected by
140                  the corresponding pin groups. The following are the list of
141                  pinmux functions available:
142
143                  eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
144                  uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
145                  pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0,
146                  sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds,
147                  usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0,
148                  nand1, spdif, sirq0, sirq1, sirq2
149
150Optional Properties:
151
152- bias-bus-hold:  No arguments. The specified pins should retain the previous
153                  state value.
154- bias-high-impedance: No arguments. The specified pins should be configured
155                  as high impedance.
156- bias-pull-down: No arguments. The specified pins should be configured as
157                  pull down.
158- bias-pull-up:   No arguments. The specified pins should be configured as
159                  pull up.
160- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
161                  pins
162- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
163                  pins
164- slew-rate:      Integer. Sets slew rate for the specified pins.
165                  Valid values are:
166                  <0>  - Slow
167                  <1>  - Fast
168- drive-strength: Integer. Selects the drive strength for the specified
169                  pins in mA.
170                  Valid values are:
171                  <2>
172                  <4>
173                  <8>
174                  <12>
175
176Example:
177
178          pinctrl: pinctrl@e01b0000 {
179                  compatible = "actions,s900-pinctrl";
180                  reg = <0x0 0xe01b0000 0x0 0x1000>;
181                  clocks = <&cmu CLK_GPIO>;
182                  gpio-controller;
183                  gpio-ranges = <&pinctrl 0 0 146>;
184                  #gpio-cells = <2>;
185                  interrupt-controller;
186                  #interrupt-cells = <2>;
187                  interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
188                               <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
189                               <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
190                               <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
191                               <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
192                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
193
194                  uart2-default: uart2-default {
195                          pinmux {
196                                  groups = "lvds_oep_odn_mfp";
197                                  function = "uart2";
198                          };
199                          pinconf {
200                                  groups = "lvds_oep_odn_drv";
201                                  drive-strength = <12>;
202                          };
203                  };
204          };
205