1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Actions Semi S500 SoC pinmux & GPIO controller
8
9maintainers:
10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
12
13description: |
14  Pinmux & GPIO controller manages pin multiplexing & configuration including
15  GPIO function selection & GPIO attributes configuration. Please refer to
16  pinctrl-bindings.txt in this directory for common binding part and usage.
17
18properties:
19  compatible:
20    const: actions,s500-pinctrl
21
22  reg:
23    items:
24      - description: GPIO Output + GPIO Input + GPIO Data
25      - description: Multiplexing Control
26      - description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
27      - description: PAD Drive Capacity Select
28    minItems: 1
29    maxItems: 4
30
31  clocks:
32    maxItems: 1
33
34  gpio-controller: true
35
36  gpio-ranges:
37    maxItems: 1
38
39  '#gpio-cells':
40    description:
41      Specifies the pin number and flags, as defined in
42      include/dt-bindings/gpio/gpio.h
43    const: 2
44
45  interrupt-controller: true
46
47  '#interrupt-cells':
48    description:
49      Specifies the pin number and flags, as defined in
50      include/dt-bindings/interrupt-controller/irq.h
51    const: 2
52
53  interrupts:
54    description:
55      One interrupt per each of the 5 GPIO ports supported by the controller,
56      sorted by port number ascending order.
57    minItems: 5
58    maxItems: 5
59
60patternProperties:
61  '-pins$':
62    type: object
63    patternProperties:
64      '^(.*-)?pinmux$':
65        type: object
66        description:
67          Pinctrl node's client devices specify pin muxes using subnodes,
68          which in turn use the standard properties below.
69        $ref: pinmux-node.yaml#
70
71        properties:
72          groups:
73            description:
74              List of gpio pin groups affected by the functions specified in
75              this subnode.
76            items:
77              oneOf:
78                - enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp,
79                    rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp,
80                    rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp,
81                    i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp,
82                    ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp,
83                    ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
84                    dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp,
85                    dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp,
86                    spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp,
87                    dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
88                    uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
89                    sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
90                    uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp,
91                    uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp,
92                    pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp,
93                    dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp,
94                    nand_ceb3_mfp]
95            minItems: 1
96            maxItems: 32
97
98          function:
99            description:
100              Specify the alternative function to be configured for the
101              given gpio pin groups.
102            enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
103              sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0,
104              i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
105              p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m,
106              mipi_csi, nand, spdif, ts, lcd0]
107
108        required:
109          - groups
110          - function
111
112        additionalProperties: false
113
114      '^(.*-)?pinconf$':
115        type: object
116        description:
117          Pinctrl node's client devices specify pin configurations using
118          subnodes, which in turn use the standard properties below.
119        $ref: pincfg-node.yaml#
120
121        properties:
122          groups:
123            description:
124              List of gpio pin groups affected by the drive-strength property
125              specified in this subnode.
126            items:
127              oneOf:
128                - enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv,
129                    rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv,
130                    smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv,
131                    i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv,
132                    lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv,
133                    sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv,
134                    spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv,
135                    i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv,
136                    sens0_ckout_drv, uart3_all_drv]
137            minItems: 1
138            maxItems: 32
139
140          pins:
141            description:
142              List of gpio pins affected by the bias-pull-* and
143              input-schmitt-* properties specified in this subnode.
144            items:
145              oneOf:
146                - enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen,
147                    eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk,
148                    eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
149                    i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1,
150                    i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1,
151                    ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
152                    lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep,
153                    lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp,
154                    lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3,
155                    dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0,
156                    dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
157                    sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
158                    spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
159                    uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk,
160                    sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1,
161                    dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb,
162                    uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb,
163                    pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk,
164                    i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0,
165                    csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
166                    csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3,
167                    dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb,
168                    dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1,
169                    pkg2, pkg3]
170            minItems: 1
171            maxItems: 64
172
173          bias-pull-up: true
174          bias-pull-down: true
175
176          drive-strength:
177            description:
178              Selects the drive strength for the specified pins, in mA.
179            enum: [2, 4, 8, 12]
180
181          input-schmitt-enable: true
182          input-schmitt-disable: true
183
184        additionalProperties: false
185
186    additionalProperties: false
187
188required:
189  - compatible
190  - reg
191  - clocks
192  - gpio-controller
193  - gpio-ranges
194  - '#gpio-cells'
195  - interrupt-controller
196  - '#interrupt-cells'
197  - interrupts
198
199additionalProperties: false
200
201examples:
202  - |
203    #include <dt-bindings/interrupt-controller/arm-gic.h>
204    pinctrl: pinctrl@b01b0000 {
205        compatible = "actions,s500-pinctrl";
206        reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>,
207              <0xb01b0060 0x18>, <0xb01b0080 0xc>;
208        clocks = <&cmu 55>;
209        gpio-controller;
210        gpio-ranges = <&pinctrl 0 0 132>;
211        #gpio-cells = <2>;
212        interrupt-controller;
213        #interrupt-cells = <2>;
214        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
215                     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
216                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
217                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
218                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
219
220        mmc0_pins: mmc0-pins {
221            pinmux {
222                groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
223                         "sd0_cmd_mfp", "sd0_clk_mfp";
224                function = "sd0";
225            };
226
227            drv-pinconf {
228                groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
229                drive-strength = <8>;
230            };
231
232            bias-pinconf {
233                pins = "sd0_d0", "sd0_d1", "sd0_d2",
234                       "sd0_d3", "sd0_cmd";
235                bias-pull-up;
236            };
237        };
238    };
239
240...
241