1TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
2
3OMAP CONTROL PHY
4
5Required properties:
6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
9                        e.g. USB2_PHY on OMAP5.
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
11                        e.g. USB3 PHY and SATA PHY on OMAP5.
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
13			set PCS delay value.
14			e.g. PCIE PHY in DRA7x
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
16                        DRA7 platform.
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
18                        AM437 platform.
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
21	      "power", "pcie_pcs" and "control_sma" for control-phy-pcie
22	      "power" for all other types
23
24omap_control_usb: omap-control-usb@4a002300 {
25        compatible = "ti,control-phy-otghs";
26        reg = <0x4a00233c 0x4>;
27        reg-names = "otghs_control";
28};
29
30OMAP USB2 PHY
31
32Required properties:
33 - compatible: Should be "ti,omap-usb2"
34	       Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
35	       in DRA7x
36 - reg : Address and length of the register set for the device.
37 - #phy-cells: determine the number of cells that should be given in the
38   phandle while referencing this phy.
39 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
40   clock-names.
41 - clock-names: should include:
42   * "wkupclk" - wakeup clock.
43   * "refclk" - reference clock (optional).
44
45Deprecated properties:
46 - ctrl-module : phandle of the control module used by PHY driver to power on
47   the PHY.
48
49Recommended properies:
50- syscon-phy-power : phandle/offset pair. Phandle to the system control
51  module and the register offset to power on/off the PHY.
52
53This is usually a subnode of ocp2scp to which it is connected.
54
55usb2phy@4a0ad080 {
56	compatible = "ti,omap-usb2";
57	reg = <0x4a0ad080 0x58>;
58	ctrl-module = <&omap_control_usb>;
59	#phy-cells = <0>;
60	clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
61	clock-names = "wkupclk", "refclk";
62};
63
64TI PIPE3 PHY
65
66Required properties:
67 - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
68   "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
69 - reg : Address and length of the register set for the device.
70 - reg-names: The names of the register addresses corresponding to the registers
71   filled in "reg".
72 - #phy-cells: determine the number of cells that should be given in the
73   phandle while referencing this phy.
74 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
75   clock-names.
76 - clock-names: should include:
77   * "wkupclk" - wakeup clock.
78   * "sysclk" - system clock.
79   * "refclk" - reference clock.
80   * "dpll_ref" - external dpll ref clk
81   * "dpll_ref_m2" - external dpll ref clk
82   * "phy-div" - divider for apll
83   * "div-clk" - apll clock
84
85Optional properties:
86 - id: If there are multiple instance of the same type, in order to
87   differentiate between each instance "id" can be used (e.g., multi-lane PCIe
88   PHY). If "id" is not provided, it is set to default value of '1'.
89 - syscon-pllreset: Handle to system control region that contains the
90   CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
91   register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
92 - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
93   register offset to write the PCS delay value.
94
95Deprecated properties:
96 - ctrl-module : phandle of the control module used by PHY driver to power on
97   the PHY.
98
99Recommended properies:
100 - syscon-phy-power : phandle/offset pair. Phandle to the system control
101   module and the register offset to power on/off the PHY.
102
103This is usually a subnode of ocp2scp to which it is connected.
104
105usb3phy@4a084400 {
106	compatible = "ti,phy-usb3";
107	reg = <0x4a084400 0x80>,
108	      <0x4a084800 0x64>,
109	      <0x4a084c00 0x40>;
110	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
111	ctrl-module = <&omap_control_usb>;
112	#phy-cells = <0>;
113	clocks = <&usb_phy_cm_clk32k>,
114		 <&sys_clkin>,
115		 <&usb_otg_ss_refclk960m>;
116	clock-names =	"wkupclk",
117			"sysclk",
118			"refclk";
119};
120
121sata_phy: phy@4A096000 {
122	compatible = "ti,phy-pipe3-sata";
123	reg = <0x4A096000 0x80>, /* phy_rx */
124	      <0x4A096400 0x64>, /* phy_tx */
125	      <0x4A096800 0x40>; /* pll_ctrl */
126	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
127	ctrl-module = <&omap_control_sata>;
128	clocks = <&sys_clkin1>, <&sata_ref_clk>;
129	clock-names = "sysclk", "refclk";
130	syscon-pllreset = <&scm_conf 0x3fc>;
131	#phy-cells = <0>;
132};
133