1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI J721E WIZ (SERDES Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13properties:
14  compatible:
15    enum:
16      - ti,j721e-wiz-16g
17      - ti,j721e-wiz-10g
18      - ti,am64-wiz-10g
19      - ti,j7200-wiz-10g
20
21  power-domains:
22    maxItems: 1
23
24  clocks:
25    minItems: 3
26    maxItems: 4
27    description: clock-specifier to represent input to the WIZ
28
29  clock-names:
30    minItems: 3
31    items:
32      - const: fck
33      - const: core_ref_clk
34      - const: ext_ref_clk
35      - const: core_ref1_clk
36
37  num-lanes:
38    minimum: 1
39    maximum: 4
40
41  "#address-cells":
42    const: 1
43
44  "#size-cells":
45    const: 1
46
47  "#reset-cells":
48    const: 1
49
50  "#clock-cells":
51    const: 1
52
53  ranges: true
54
55  assigned-clocks:
56    minItems: 1
57    maxItems: 2
58
59  assigned-clock-parents:
60    minItems: 1
61    maxItems: 2
62
63  assigned-clock-rates:
64    minItems: 1
65    maxItems: 2
66
67  typec-dir-gpios:
68    maxItems: 1
69    description:
70      GPIO to signal Type-C cable orientation for lane swap.
71      If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
72      achieve the funtionality of an external type-C plug flip mux.
73
74  typec-dir-debounce-ms:
75    minimum: 100
76    maximum: 1000
77    default: 100
78    description:
79      Number of milliseconds to wait before sampling typec-dir-gpio.
80      If not specified, the default debounce of 100ms will be used.
81      Type-C spec states minimum CC pin debounce of 100 ms and maximum
82      of 200 ms. However, some solutions might need more than 200 ms.
83
84  refclk-dig:
85    type: object
86    additionalProperties: false
87    description: |
88      WIZ node should have subnode for refclk_dig to select the reference
89      clock source for the reference clock used in the PHY and PMA digital
90      logic.
91    deprecated: true
92    properties:
93      clocks:
94        minItems: 2
95        maxItems: 4
96        description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
97          the inputs to refclk_dig
98
99      "#clock-cells":
100        const: 0
101
102      assigned-clocks:
103        maxItems: 1
104
105      assigned-clock-parents:
106        maxItems: 1
107
108    required:
109      - clocks
110      - "#clock-cells"
111      - assigned-clocks
112      - assigned-clock-parents
113
114  ti,scm:
115    $ref: /schemas/types.yaml#/definitions/phandle
116    description: |
117      phandle to System Control Module for syscon regmap access.
118
119patternProperties:
120  "^pll[0|1]-refclk$":
121    type: object
122    additionalProperties: false
123    description: |
124      WIZ node should have subnodes for each of the PLLs present in
125      the SERDES.
126    deprecated: true
127    properties:
128      clocks:
129        maxItems: 2
130        description: Phandle to clock nodes representing the two inputs to PLL.
131
132      "#clock-cells":
133        const: 0
134
135      assigned-clocks:
136        maxItems: 1
137
138      assigned-clock-parents:
139        maxItems: 1
140
141    required:
142      - clocks
143      - "#clock-cells"
144      - assigned-clocks
145      - assigned-clock-parents
146
147  "^cmn-refclk1?-dig-div$":
148    type: object
149    additionalProperties: false
150    description:
151      WIZ node should have subnodes for each of the PMA common refclock
152      provided by the SERDES.
153    deprecated: true
154    properties:
155      clocks:
156        maxItems: 1
157        description: Phandle to the clock node representing the input to the
158          divider clock.
159
160      "#clock-cells":
161        const: 0
162
163    required:
164      - clocks
165      - "#clock-cells"
166
167  "^serdes@[0-9a-f]+$":
168    type: object
169    description: |
170      WIZ node should have '1' subnode for the SERDES. It could be either
171      Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
172      bindings specified in
173      Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
174      Torrent SERDES should follow the bindings specified in
175      Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
176
177required:
178  - compatible
179  - power-domains
180  - clocks
181  - clock-names
182  - num-lanes
183  - "#address-cells"
184  - "#size-cells"
185  - "#reset-cells"
186  - ranges
187
188allOf:
189  - if:
190      properties:
191        compatible:
192          contains:
193            const: ti,j7200-wiz-10g
194    then:
195      required:
196        - ti,scm
197
198additionalProperties: false
199
200examples:
201  - |
202    #include <dt-bindings/soc/ti,sci_pm_domain.h>
203
204    wiz@5000000 {
205           compatible = "ti,j721e-wiz-16g";
206           #address-cells = <1>;
207           #size-cells = <1>;
208           power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
209           clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
210           clock-names = "fck", "core_ref_clk", "ext_ref_clk";
211           assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
212           assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
213           num-lanes = <2>;
214           #reset-cells = <1>;
215           ranges = <0x5000000 0x5000000 0x10000>;
216
217           pll0-refclk {
218                  clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
219                  #clock-cells = <0>;
220                  assigned-clocks = <&wiz1_pll0_refclk>;
221                  assigned-clock-parents = <&k3_clks 293 13>;
222           };
223
224           pll1-refclk {
225                  clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
226                  #clock-cells = <0>;
227                  assigned-clocks = <&wiz1_pll1_refclk>;
228                  assigned-clock-parents = <&k3_clks 293 0>;
229           };
230
231           cmn-refclk-dig-div {
232                  clocks = <&wiz1_refclk_dig>;
233                  #clock-cells = <0>;
234           };
235
236           cmn-refclk1-dig-div {
237                  clocks = <&wiz1_pll1_refclk>;
238                  #clock-cells = <0>;
239           };
240
241           refclk-dig {
242                  clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
243                          <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
244                  #clock-cells = <0>;
245                  assigned-clocks = <&wiz0_refclk_dig>;
246                  assigned-clock-parents = <&k3_clks 292 11>;
247           };
248
249           serdes@5000000 {
250                  compatible = "ti,sierra-phy-t0";
251                  reg-names = "serdes";
252                  reg = <0x5000000 0x10000>;
253                  #address-cells = <1>;
254                  #size-cells = <0>;
255                  resets = <&serdes_wiz0 0>;
256                  reset-names = "sierra_reset";
257                  clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
258                  clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
259           };
260    };
261