1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier USB3 High-Speed (HS) PHY
8
9description: |
10  This describes the devicetree bindings for PHY interfaces built into
11  USB3 controller implemented on Socionext UniPhier SoCs.
12  Although the controller includes High-Speed PHY and Super-Speed PHY,
13  this describes about High-Speed PHY.
14
15maintainers:
16  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17
18properties:
19  compatible:
20    enum:
21      - socionext,uniphier-pro5-usb3-hsphy
22      - socionext,uniphier-pxs2-usb3-hsphy
23      - socionext,uniphier-ld20-usb3-hsphy
24      - socionext,uniphier-pxs3-usb3-hsphy
25      - socionext,uniphier-nx1-usb3-hsphy
26
27  reg:
28    maxItems: 1
29
30  "#phy-cells":
31    const: 0
32
33  clocks:
34    minItems: 2
35    maxItems: 3
36
37  clock-names:
38    oneOf:
39      - items:               # for Pro5
40          - const: gio
41          - const: link
42      - items:               # for PXs3 with phy-ext
43          - const: link
44          - const: phy
45          - const: phy-ext
46      - items:               # for others
47          - const: link
48          - const: phy
49
50  resets:
51    maxItems: 2
52
53  reset-names:
54    oneOf:
55      - items:               # for Pro5
56          - const: gio
57          - const: link
58      - items:               # for others
59          - const: link
60          - const: phy
61
62  vbus-supply:
63    description: A phandle to the regulator for USB VBUS
64
65  nvmem-cells:
66    maxItems: 3
67    description:
68      Phandles to nvmem cell that contains the trimming data.
69      Available only for HS-PHY implemented on LD20 and PXs3, and
70      if unspecified, default value is used.
71
72  nvmem-cell-names:
73    items:
74      - const: rterm
75      - const: sel_t
76      - const: hs_i
77    description:
78      Should be the following names, which correspond to each nvmem-cells.
79      All of the 3 parameters associated with the above names are
80      required for each port, if any one is omitted, the trimming data
81      of the port will not be set at all.
82
83required:
84  - compatible
85  - reg
86  - "#phy-cells"
87  - clocks
88  - clock-names
89  - resets
90  - reset-names
91
92additionalProperties: false
93
94examples:
95  - |
96    usb-glue@65b00000 {
97        compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
98        #address-cells = <1>;
99        #size-cells = <1>;
100        ranges = <0 0x65b00000 0x400>;
101
102        usb_hsphy0: hs-phy@200 {
103            compatible = "socionext,uniphier-ld20-usb3-hsphy";
104            reg = <0x200 0x10>;
105            #phy-cells = <0>;
106            clock-names = "link", "phy";
107            clocks = <&sys_clk 14>, <&sys_clk 16>;
108            reset-names = "link", "phy";
109            resets = <&sys_rst 14>, <&sys_rst 16>;
110            vbus-supply = <&usb_vbus0>;
111            nvmem-cell-names = "rterm", "sel_t", "hs_i";
112            nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
113        };
114    };
115