1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier USB3 High-Speed (HS) PHY
8
9description: |
10  This describes the devicetree bindings for PHY interfaces built into
11  USB3 controller implemented on Socionext UniPhier SoCs.
12  Although the controller includes High-Speed PHY and Super-Speed PHY,
13  this describes about High-Speed PHY.
14
15maintainers:
16  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17
18properties:
19  compatible:
20    enum:
21      - socionext,uniphier-pro5-usb3-hsphy
22      - socionext,uniphier-pxs2-usb3-hsphy
23      - socionext,uniphier-ld20-usb3-hsphy
24      - socionext,uniphier-pxs3-usb3-hsphy
25
26  reg:
27    description: PHY register region (offset and length)
28
29  "#phy-cells":
30    const: 0
31
32  clocks:
33    minItems: 1
34    maxItems: 2
35
36  clock-names:
37    oneOf:
38      - const: link          # for PXs2
39      - items:               # for PXs3
40        - const: link
41        - const: phy
42
43  resets:
44    maxItems: 2
45
46  reset-names:
47    items:
48      - const: link
49      - const: phy
50
51  vbus-supply:
52    description: A phandle to the regulator for USB VBUS
53
54  nvmem-cells:
55    maxItems: 3
56    description:
57      Phandles to nvmem cell that contains the trimming data.
58      Available only for HS-PHY implemented on LD20 and PXs3, and
59      if unspecified, default value is used.
60
61  nvmem-cell-names:
62    items:
63      - const: rterm
64      - const: sel_t
65      - const: hs_i
66    description:
67      Should be the following names, which correspond to each nvmem-cells.
68      All of the 3 parameters associated with the above names are
69      required for each port, if any one is omitted, the trimming data
70      of the port will not be set at all.
71
72required:
73  - compatible
74  - reg
75  - "#phy-cells"
76  - clocks
77  - clock-names
78  - resets
79  - reset-names
80
81additionalProperties: false
82
83examples:
84  - |
85    usb-glue@65b00000 {
86        compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
87        #address-cells = <1>;
88        #size-cells = <1>;
89        ranges = <0 0x65b00000 0x400>;
90
91        usb_hsphy0: hs-phy@200 {
92            compatible = "socionext,uniphier-ld20-usb3-hsphy";
93            reg = <0x200 0x10>;
94            #phy-cells = <0>;
95            clock-names = "link", "phy";
96            clocks = <&sys_clk 14>, <&sys_clk 16>;
97            reset-names = "link", "phy";
98            resets = <&sys_rst 14>, <&sys_rst 16>;
99            vbus-supply = <&usb_vbus0>;
100            nvmem-cell-names = "rterm", "sel_t", "hs_i";
101            nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
102        };
103    };
104