1134ab284SKunihiko Hayashi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2134ab284SKunihiko Hayashi%YAML 1.2 3134ab284SKunihiko Hayashi--- 4134ab284SKunihiko Hayashi$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml# 5134ab284SKunihiko Hayashi$schema: http://devicetree.org/meta-schemas/core.yaml# 6134ab284SKunihiko Hayashi 7134ab284SKunihiko Hayashititle: Socionext UniPhier USB3 High-Speed (HS) PHY 8134ab284SKunihiko Hayashi 9134ab284SKunihiko Hayashidescription: | 10134ab284SKunihiko Hayashi This describes the devicetree bindings for PHY interfaces built into 11134ab284SKunihiko Hayashi USB3 controller implemented on Socionext UniPhier SoCs. 12134ab284SKunihiko Hayashi Although the controller includes High-Speed PHY and Super-Speed PHY, 13134ab284SKunihiko Hayashi this describes about High-Speed PHY. 14134ab284SKunihiko Hayashi 15134ab284SKunihiko Hayashimaintainers: 16134ab284SKunihiko Hayashi - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 17134ab284SKunihiko Hayashi 18134ab284SKunihiko Hayashiproperties: 19134ab284SKunihiko Hayashi compatible: 20134ab284SKunihiko Hayashi enum: 21134ab284SKunihiko Hayashi - socionext,uniphier-pro5-usb3-hsphy 22134ab284SKunihiko Hayashi - socionext,uniphier-pxs2-usb3-hsphy 23134ab284SKunihiko Hayashi - socionext,uniphier-ld20-usb3-hsphy 24134ab284SKunihiko Hayashi - socionext,uniphier-pxs3-usb3-hsphy 25134ab284SKunihiko Hayashi 26134ab284SKunihiko Hayashi reg: 27134ab284SKunihiko Hayashi description: PHY register region (offset and length) 28134ab284SKunihiko Hayashi 29134ab284SKunihiko Hayashi "#phy-cells": 30134ab284SKunihiko Hayashi const: 0 31134ab284SKunihiko Hayashi 32134ab284SKunihiko Hayashi clocks: 33134ab284SKunihiko Hayashi minItems: 1 34134ab284SKunihiko Hayashi maxItems: 2 35134ab284SKunihiko Hayashi 36134ab284SKunihiko Hayashi clock-names: 37134ab284SKunihiko Hayashi oneOf: 38134ab284SKunihiko Hayashi - const: link # for PXs2 39134ab284SKunihiko Hayashi - items: # for PXs3 40134ab284SKunihiko Hayashi - const: link 41134ab284SKunihiko Hayashi - const: phy 42134ab284SKunihiko Hayashi 43134ab284SKunihiko Hayashi resets: 44134ab284SKunihiko Hayashi maxItems: 2 45134ab284SKunihiko Hayashi 46134ab284SKunihiko Hayashi reset-names: 47134ab284SKunihiko Hayashi items: 48134ab284SKunihiko Hayashi - const: link 49134ab284SKunihiko Hayashi - const: phy 50134ab284SKunihiko Hayashi 51134ab284SKunihiko Hayashi vbus-supply: 52134ab284SKunihiko Hayashi description: A phandle to the regulator for USB VBUS 53134ab284SKunihiko Hayashi 54134ab284SKunihiko Hayashi nvmem-cells: 55134ab284SKunihiko Hayashi maxItems: 3 56134ab284SKunihiko Hayashi description: 57134ab284SKunihiko Hayashi Phandles to nvmem cell that contains the trimming data. 58134ab284SKunihiko Hayashi Available only for HS-PHY implemented on LD20 and PXs3, and 59134ab284SKunihiko Hayashi if unspecified, default value is used. 60134ab284SKunihiko Hayashi 61134ab284SKunihiko Hayashi nvmem-cell-names: 62134ab284SKunihiko Hayashi items: 63134ab284SKunihiko Hayashi - const: rterm 64134ab284SKunihiko Hayashi - const: sel_t 65134ab284SKunihiko Hayashi - const: hs_i 66134ab284SKunihiko Hayashi description: 67134ab284SKunihiko Hayashi Should be the following names, which correspond to each nvmem-cells. 68134ab284SKunihiko Hayashi All of the 3 parameters associated with the above names are 69134ab284SKunihiko Hayashi required for each port, if any one is omitted, the trimming data 70134ab284SKunihiko Hayashi of the port will not be set at all. 71134ab284SKunihiko Hayashi 72134ab284SKunihiko Hayashirequired: 73134ab284SKunihiko Hayashi - compatible 74134ab284SKunihiko Hayashi - reg 75134ab284SKunihiko Hayashi - "#phy-cells" 76134ab284SKunihiko Hayashi - clocks 77134ab284SKunihiko Hayashi - clock-names 78134ab284SKunihiko Hayashi - resets 79134ab284SKunihiko Hayashi - reset-names 80134ab284SKunihiko Hayashi 81134ab284SKunihiko HayashiadditionalProperties: false 82134ab284SKunihiko Hayashi 83134ab284SKunihiko Hayashiexamples: 84134ab284SKunihiko Hayashi - | 85134ab284SKunihiko Hayashi usb-glue@65b00000 { 86134ab284SKunihiko Hayashi compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd"; 87134ab284SKunihiko Hayashi #address-cells = <1>; 88134ab284SKunihiko Hayashi #size-cells = <1>; 89134ab284SKunihiko Hayashi ranges = <0 0x65b00000 0x400>; 90134ab284SKunihiko Hayashi 91134ab284SKunihiko Hayashi usb_hsphy0: hs-phy@200 { 92134ab284SKunihiko Hayashi compatible = "socionext,uniphier-ld20-usb3-hsphy"; 93134ab284SKunihiko Hayashi reg = <0x200 0x10>; 94134ab284SKunihiko Hayashi #phy-cells = <0>; 95134ab284SKunihiko Hayashi clock-names = "link", "phy"; 96134ab284SKunihiko Hayashi clocks = <&sys_clk 14>, <&sys_clk 16>; 97134ab284SKunihiko Hayashi reset-names = "link", "phy"; 98134ab284SKunihiko Hayashi resets = <&sys_rst 14>, <&sys_rst 16>; 99134ab284SKunihiko Hayashi vbus-supply = <&usb_vbus0>; 100134ab284SKunihiko Hayashi nvmem-cell-names = "rterm", "sel_t", "hs_i"; 101134ab284SKunihiko Hayashi nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>; 102134ab284SKunihiko Hayashi }; 103134ab284SKunihiko Hayashi }; 104