bindings/phy/socionext%2Cuniphier-pcie-phy.yaml

b36a2472SKunihiko Hayashi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
b36a2472SKunihiko Hayashi%YAML 1.2
b36a2472SKunihiko Hayashi---
b36a2472SKunihiko Hayashi$id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
b36a2472SKunihiko Hayashi$schema: http://devicetree.org/meta-schemas/core.yaml#
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashititle: Socionext UniPhier PCIe PHY
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashidescription: |
b36a2472SKunihiko Hayashi  This describes the devicetree bindings for PHY interface built into
b36a2472SKunihiko Hayashi  PCIe controller implemented on Socionext UniPhier SoCs.
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashimaintainers:
b36a2472SKunihiko Hayashi  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashiproperties:
b36a2472SKunihiko Hayashi  compatible:
b36a2472SKunihiko Hayashi    enum:
b36a2472SKunihiko Hayashi      - socionext,uniphier-pro5-pcie-phy
b36a2472SKunihiko Hayashi      - socionext,uniphier-ld20-pcie-phy
b36a2472SKunihiko Hayashi      - socionext,uniphier-pxs3-pcie-phy
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashi  reg:
b36a2472SKunihiko Hayashi    description: PHY register region (offset and length)
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashi  "#phy-cells":
b36a2472SKunihiko Hayashi    const: 0
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashi  clocks:
b36a2472SKunihiko Hayashi    minItems: 1
b36a2472SKunihiko Hayashi    maxItems: 2
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashi  clock-names:
b36a2472SKunihiko Hayashi    oneOf:
b36a2472SKunihiko Hayashi      - items:            # for Pro5
b36a2472SKunihiko Hayashi        - const: gio
b36a2472SKunihiko Hayashi        - const: link
b36a2472SKunihiko Hayashi      - const: link       # for others
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashi  resets:
b36a2472SKunihiko Hayashi    minItems: 1
b36a2472SKunihiko Hayashi    maxItems: 2
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashi  reset-names:
b36a2472SKunihiko Hayashi    oneOf:
b36a2472SKunihiko Hayashi      - items:            # for Pro5
b36a2472SKunihiko Hayashi        - const: gio
b36a2472SKunihiko Hayashi        - const: link
b36a2472SKunihiko Hayashi      - const: link       # for others
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashi  socionext,syscon:
b36a2472SKunihiko Hayashi    $ref: /schemas/types.yaml#/definitions/phandle
b36a2472SKunihiko Hayashi    description: A phandle to system control to set configurations for phy
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashirequired:
b36a2472SKunihiko Hayashi  - compatible
b36a2472SKunihiko Hayashi  - reg
b36a2472SKunihiko Hayashi  - "#phy-cells"
b36a2472SKunihiko Hayashi  - clocks
b36a2472SKunihiko Hayashi  - clock-names
b36a2472SKunihiko Hayashi  - resets
b36a2472SKunihiko Hayashi  - reset-names
b36a2472SKunihiko Hayashi
b36a2472SKunihiko HayashiadditionalProperties: false
b36a2472SKunihiko Hayashi
b36a2472SKunihiko Hayashiexamples:
b36a2472SKunihiko Hayashi  - |
b36a2472SKunihiko Hayashi    pcie_phy: phy@66038000 {
b36a2472SKunihiko Hayashi        compatible = "socionext,uniphier-ld20-pcie-phy";
b36a2472SKunihiko Hayashi        reg = <0x66038000 0x4000>;
b36a2472SKunihiko Hayashi        #phy-cells = <0>;
b36a2472SKunihiko Hayashi        clock-names = "link";
b36a2472SKunihiko Hayashi        clocks = <&sys_clk 24>;
b36a2472SKunihiko Hayashi        reset-names = "link";
b36a2472SKunihiko Hayashi        resets = <&sys_rst 24>;
b36a2472SKunihiko Hayashi        socionext,syscon = <&soc_glue>;
b36a2472SKunihiko Hayashi    };