1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Rockchip MIPI DPHY with additional LVDS/TTL modes 8 9maintainers: 10 - Heiko Stuebner <heiko@sntech.de> 11 12properties: 13 "#phy-cells": 14 const: 0 15 16 "#clock-cells": 17 const: 0 18 19 compatible: 20 enum: 21 - rockchip,px30-dsi-dphy 22 - rockchip,rk3128-dsi-dphy 23 - rockchip,rk3368-dsi-dphy 24 25 reg: 26 maxItems: 1 27 28 clocks: 29 items: 30 - description: PLL reference clock 31 - description: Module clock 32 33 clock-names: 34 items: 35 - const: ref 36 - const: pclk 37 38 power-domains: 39 maxItems: 1 40 description: phandle to the associated power domain 41 42 resets: 43 items: 44 - description: exclusive PHY reset line 45 46 reset-names: 47 items: 48 - const: apb 49 50required: 51 - "#phy-cells" 52 - "#clock-cells" 53 - compatible 54 - reg 55 - clocks 56 - clock-names 57 - resets 58 - reset-names 59 60additionalProperties: false 61 62examples: 63 - | 64 dsi_dphy: phy@ff2e0000 { 65 compatible = "rockchip,px30-video-phy"; 66 reg = <0x0 0xff2e0000 0x0 0x10000>; 67 clocks = <&pmucru 13>, <&cru 12>; 68 clock-names = "ref", "pclk"; 69 #clock-cells = <0>; 70 resets = <&cru 12>; 71 reset-names = "apb"; 72 #phy-cells = <0>; 73 }; 74 75... 76