1*75be98eeSFrank Wunderlich# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*75be98eeSFrank Wunderlich%YAML 1.2 3*75be98eeSFrank Wunderlich--- 4*75be98eeSFrank Wunderlich$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# 5*75be98eeSFrank Wunderlich$schema: http://devicetree.org/meta-schemas/core.yaml# 6*75be98eeSFrank Wunderlich 7*75be98eeSFrank Wunderlichtitle: Rockchip PCIe v3 phy 8*75be98eeSFrank Wunderlich 9*75be98eeSFrank Wunderlichmaintainers: 10*75be98eeSFrank Wunderlich - Heiko Stuebner <heiko@sntech.de> 11*75be98eeSFrank Wunderlich 12*75be98eeSFrank Wunderlichproperties: 13*75be98eeSFrank Wunderlich compatible: 14*75be98eeSFrank Wunderlich enum: 15*75be98eeSFrank Wunderlich - rockchip,rk3568-pcie3-phy 16*75be98eeSFrank Wunderlich 17*75be98eeSFrank Wunderlich reg: 18*75be98eeSFrank Wunderlich maxItems: 1 19*75be98eeSFrank Wunderlich 20*75be98eeSFrank Wunderlich clocks: 21*75be98eeSFrank Wunderlich minItems: 3 22*75be98eeSFrank Wunderlich maxItems: 3 23*75be98eeSFrank Wunderlich 24*75be98eeSFrank Wunderlich clock-names: 25*75be98eeSFrank Wunderlich items: 26*75be98eeSFrank Wunderlich - const: refclk_m 27*75be98eeSFrank Wunderlich - const: refclk_n 28*75be98eeSFrank Wunderlich - const: pclk 29*75be98eeSFrank Wunderlich 30*75be98eeSFrank Wunderlich data-lanes: 31*75be98eeSFrank Wunderlich description: which lanes (by position) should be mapped to which 32*75be98eeSFrank Wunderlich controller (value). 0 means lane disabled, higher value means used. 33*75be98eeSFrank Wunderlich (controller-number +1 ) 34*75be98eeSFrank Wunderlich $ref: /schemas/types.yaml#/definitions/uint32-array 35*75be98eeSFrank Wunderlich minItems: 2 36*75be98eeSFrank Wunderlich maxItems: 16 37*75be98eeSFrank Wunderlich items: 38*75be98eeSFrank Wunderlich minimum: 0 39*75be98eeSFrank Wunderlich maximum: 16 40*75be98eeSFrank Wunderlich 41*75be98eeSFrank Wunderlich "#phy-cells": 42*75be98eeSFrank Wunderlich const: 0 43*75be98eeSFrank Wunderlich 44*75be98eeSFrank Wunderlich resets: 45*75be98eeSFrank Wunderlich maxItems: 1 46*75be98eeSFrank Wunderlich 47*75be98eeSFrank Wunderlich reset-names: 48*75be98eeSFrank Wunderlich const: phy 49*75be98eeSFrank Wunderlich 50*75be98eeSFrank Wunderlich rockchip,phy-grf: 51*75be98eeSFrank Wunderlich $ref: /schemas/types.yaml#/definitions/phandle 52*75be98eeSFrank Wunderlich description: phandle to the syscon managing the phy "general register files" 53*75be98eeSFrank Wunderlich 54*75be98eeSFrank Wunderlich rockchip,pipe-grf: 55*75be98eeSFrank Wunderlich $ref: /schemas/types.yaml#/definitions/phandle 56*75be98eeSFrank Wunderlich description: phandle to the syscon managing the pipe "general register files" 57*75be98eeSFrank Wunderlich 58*75be98eeSFrank Wunderlichrequired: 59*75be98eeSFrank Wunderlich - compatible 60*75be98eeSFrank Wunderlich - reg 61*75be98eeSFrank Wunderlich - rockchip,phy-grf 62*75be98eeSFrank Wunderlich - "#phy-cells" 63*75be98eeSFrank Wunderlich 64*75be98eeSFrank WunderlichadditionalProperties: false 65*75be98eeSFrank Wunderlich 66*75be98eeSFrank Wunderlichexamples: 67*75be98eeSFrank Wunderlich - | 68*75be98eeSFrank Wunderlich #include <dt-bindings/clock/rk3568-cru.h> 69*75be98eeSFrank Wunderlich pcie30phy: phy@fe8c0000 { 70*75be98eeSFrank Wunderlich compatible = "rockchip,rk3568-pcie3-phy"; 71*75be98eeSFrank Wunderlich reg = <0xfe8c0000 0x20000>; 72*75be98eeSFrank Wunderlich #phy-cells = <0>; 73*75be98eeSFrank Wunderlich clocks = <&pmucru CLK_PCIE30PHY_REF_M>, 74*75be98eeSFrank Wunderlich <&pmucru CLK_PCIE30PHY_REF_N>, 75*75be98eeSFrank Wunderlich <&cru PCLK_PCIE30PHY>; 76*75be98eeSFrank Wunderlich clock-names = "refclk_m", "refclk_n", "pclk"; 77*75be98eeSFrank Wunderlich resets = <&cru SRST_PCIE30PHY>; 78*75be98eeSFrank Wunderlich reset-names = "phy"; 79*75be98eeSFrank Wunderlich rockchip,phy-grf = <&pcie30_phy_grf>; 80*75be98eeSFrank Wunderlich }; 81