1*8a981128SGeert Uytterhoeven# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*8a981128SGeert Uytterhoeven%YAML 1.2 3*8a981128SGeert Uytterhoeven--- 4*8a981128SGeert Uytterhoeven$id: http://devicetree.org/schemas/phy/renesas,rcar-gen3-pcie-phy.yaml# 5*8a981128SGeert Uytterhoeven$schema: http://devicetree.org/meta-schemas/core.yaml# 6*8a981128SGeert Uytterhoeven 7*8a981128SGeert Uytterhoeventitle: Renesas R-Car Generation 3 PCIe PHY 8*8a981128SGeert Uytterhoeven 9*8a981128SGeert Uytterhoevenmaintainers: 10*8a981128SGeert Uytterhoeven - Sergei Shtylyov <sergei.shtylyov@gmail.com> 11*8a981128SGeert Uytterhoeven 12*8a981128SGeert Uytterhoevenproperties: 13*8a981128SGeert Uytterhoeven compatible: 14*8a981128SGeert Uytterhoeven const: renesas,r8a77980-pcie-phy 15*8a981128SGeert Uytterhoeven 16*8a981128SGeert Uytterhoeven reg: 17*8a981128SGeert Uytterhoeven maxItems: 1 18*8a981128SGeert Uytterhoeven 19*8a981128SGeert Uytterhoeven clocks: 20*8a981128SGeert Uytterhoeven maxItems: 1 21*8a981128SGeert Uytterhoeven 22*8a981128SGeert Uytterhoeven power-domains: 23*8a981128SGeert Uytterhoeven maxItems: 1 24*8a981128SGeert Uytterhoeven 25*8a981128SGeert Uytterhoeven resets: 26*8a981128SGeert Uytterhoeven maxItems: 1 27*8a981128SGeert Uytterhoeven 28*8a981128SGeert Uytterhoeven '#phy-cells': 29*8a981128SGeert Uytterhoeven const: 0 30*8a981128SGeert Uytterhoeven 31*8a981128SGeert Uytterhoevenrequired: 32*8a981128SGeert Uytterhoeven - compatible 33*8a981128SGeert Uytterhoeven - reg 34*8a981128SGeert Uytterhoeven - clocks 35*8a981128SGeert Uytterhoeven - power-domains 36*8a981128SGeert Uytterhoeven - resets 37*8a981128SGeert Uytterhoeven - '#phy-cells' 38*8a981128SGeert Uytterhoeven 39*8a981128SGeert UytterhoevenadditionalProperties: false 40*8a981128SGeert Uytterhoeven 41*8a981128SGeert Uytterhoevenexamples: 42*8a981128SGeert Uytterhoeven - | 43*8a981128SGeert Uytterhoeven #include <dt-bindings/clock/r8a77980-cpg-mssr.h> 44*8a981128SGeert Uytterhoeven #include <dt-bindings/power/r8a77980-sysc.h> 45*8a981128SGeert Uytterhoeven 46*8a981128SGeert Uytterhoeven pcie-phy@e65d0000 { 47*8a981128SGeert Uytterhoeven compatible = "renesas,r8a77980-pcie-phy"; 48*8a981128SGeert Uytterhoeven reg = <0xe65d0000 0x8000>; 49*8a981128SGeert Uytterhoeven #phy-cells = <0>; 50*8a981128SGeert Uytterhoeven clocks = <&cpg CPG_MOD 319>; 51*8a981128SGeert Uytterhoeven power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 52*8a981128SGeert Uytterhoeven resets = <&cpg 319>; 53*8a981128SGeert Uytterhoeven }; 54