1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: Qualcomm QUSB2 phy controller
9
10maintainers:
11  - Manu Gautam <mgautam@codeaurora.org>
12
13description:
14  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
15
16properties:
17  compatible:
18    oneOf:
19      - items:
20          - enum:
21              - qcom,ipq8074-qusb2-phy
22              - qcom,msm8996-qusb2-phy
23              - qcom,msm8998-qusb2-phy
24              - qcom,qcm2290-qusb2-phy
25              - qcom,sdm660-qusb2-phy
26              - qcom,ipq6018-qusb2-phy
27              - qcom,sm4250-qusb2-phy
28              - qcom,sm6115-qusb2-phy
29      - items:
30          - enum:
31              - qcom,sc7180-qusb2-phy
32              - qcom,sdm845-qusb2-phy
33              - qcom,sm6350-qusb2-phy
34          - const: qcom,qusb2-v2-phy
35  reg:
36    maxItems: 1
37
38  "#phy-cells":
39    const: 0
40
41  clocks:
42    minItems: 2
43    items:
44      - description: phy config clock
45      - description: 19.2 MHz ref clk
46      - description: phy interface clock (Optional)
47
48  clock-names:
49    minItems: 2
50    items:
51      - const: cfg_ahb
52      - const: ref
53      - const: iface
54
55  vdd-supply:
56    description:
57      Phandle to 0.9V regulator supply to PHY digital circuit.
58
59  vdda-pll-supply:
60    description:
61      Phandle to 1.8V regulator supply to PHY refclk pll block.
62
63  vdda-phy-dpdm-supply:
64    description:
65      Phandle to 3.1V regulator supply to Dp/Dm port signals.
66
67  resets:
68    maxItems: 1
69    description:
70      Phandle to reset to phy block.
71
72  nvmem-cells:
73    maxItems: 1
74    description:
75      Phandle to nvmem cell that contains 'HS Tx trim'
76      tuning parameter value for qusb2 phy.
77
78  qcom,tcsr-syscon:
79    description:
80      Phandle to TCSR syscon register region.
81    $ref: /schemas/types.yaml#/definitions/phandle
82
83if:
84  properties:
85    compatible:
86      contains:
87        const: qcom,qusb2-v2-phy
88then:
89  properties:
90    qcom,imp-res-offset-value:
91      description:
92        It is a 6 bit value that specifies offset to be
93        added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
94        tuning parameter that may vary for different boards of same SOC.
95      $ref: /schemas/types.yaml#/definitions/uint32
96      minimum: 0
97      maximum: 63
98      default: 0
99
100    qcom,bias-ctrl-value:
101      description:
102        It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
103        tuning parameter that may vary for different boards of same SOC.
104      $ref: /schemas/types.yaml#/definitions/uint32
105      minimum: 0
106      maximum: 63
107      default: 32
108
109    qcom,charge-ctrl-value:
110      description:
111        It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
112        tuning parameter that may vary for different boards of same SOC.
113      $ref: /schemas/types.yaml#/definitions/uint32
114      minimum: 0
115      maximum: 3
116      default: 0
117
118    qcom,hstx-trim-value:
119      description:
120        It is a 4 bit value that specifies tuning for HSTX
121        output current.
122        Possible range is - 15mA to 24mA (stepsize of 600 uA).
123        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
124      $ref: /schemas/types.yaml#/definitions/uint32
125      minimum: 0
126      maximum: 15
127      default: 3
128
129    qcom,preemphasis-level:
130      description:
131        It is a 2 bit value that specifies pre-emphasis level.
132        Possible range is 0 to 15% (stepsize of 5%).
133        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
134      $ref: /schemas/types.yaml#/definitions/uint32
135      minimum: 0
136      maximum: 3
137      default: 2
138
139    qcom,preemphasis-width:
140      description:
141        It is a 1 bit value that specifies how long the HSTX
142        pre-emphasis (specified using qcom,preemphasis-level) must be in
143        effect. Duration could be half-bit of full-bit.
144        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
145      $ref: /schemas/types.yaml#/definitions/uint32
146      minimum: 0
147      maximum: 1
148      default: 0
149
150    qcom,hsdisc-trim-value:
151      description:
152        It is a 2 bit value tuning parameter that control disconnect
153        threshold and may vary for different boards of same SOC.
154      $ref: /schemas/types.yaml#/definitions/uint32
155      minimum: 0
156      maximum: 3
157      default: 0
158
159required:
160  - compatible
161  - reg
162  - "#phy-cells"
163  - clocks
164  - clock-names
165  - vdd-supply
166  - vdda-pll-supply
167  - vdda-phy-dpdm-supply
168  - resets
169
170additionalProperties: false
171
172examples:
173  - |
174    #include <dt-bindings/clock/qcom,gcc-msm8996.h>
175    hsusb_phy: phy@7411000 {
176        compatible = "qcom,msm8996-qusb2-phy";
177        reg = <0x7411000 0x180>;
178        #phy-cells = <0>;
179
180        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
181                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
182        clock-names = "cfg_ahb", "ref";
183
184        vdd-supply = <&pm8994_l28>;
185        vdda-pll-supply = <&pm8994_l12>;
186        vdda-phy-dpdm-supply = <&pm8994_l24>;
187
188        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
189        nvmem-cells = <&qusb2p_hstx_trim>;
190    };
191