1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4
5$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Qualcomm Adreno/Snapdragon QMP HDMI phy
9
10maintainers:
11  - Rob Clark <robdclark@gmail.com>
12
13properties:
14  compatible:
15    enum:
16      - qcom,hdmi-phy-8996
17
18  reg:
19    maxItems: 6
20
21  reg-names:
22    items:
23      - const: hdmi_pll
24      - const: hdmi_tx_l0
25      - const: hdmi_tx_l1
26      - const: hdmi_tx_l2
27      - const: hdmi_tx_l3
28      - const: hdmi_phy
29
30  clocks:
31    minItems: 2
32    maxItems: 3
33
34  clock-names:
35    minItems: 2
36    items:
37      - const: iface
38      - const: ref
39      - const: xo
40
41  power-domains:
42    maxItems: 1
43
44  vcca-supply:
45    description: phandle to VCCA supply regulator
46
47  vddio-supply:
48    description: phandle to VDD I/O supply regulator
49
50  '#clock-cells':
51    const: 0
52
53  '#phy-cells':
54    const: 0
55
56required:
57  - compatible
58  - clocks
59  - clock-names
60  - reg
61  - reg-names
62  - '#phy-cells'
63
64additionalProperties: false
65
66examples:
67  - |
68    hdmi-phy@9a0600 {
69      compatible = "qcom,hdmi-phy-8996";
70      reg = <0x009a0600 0x1c4>,
71            <0x009a0a00 0x124>,
72            <0x009a0c00 0x124>,
73            <0x009a0e00 0x124>,
74            <0x009a1000 0x124>,
75            <0x009a1200 0x0c8>;
76      reg-names = "hdmi_pll",
77                  "hdmi_tx_l0",
78                  "hdmi_tx_l1",
79                  "hdmi_tx_l2",
80                  "hdmi_tx_l3",
81                  "hdmi_phy";
82
83      clocks = <&mmcc 116>,
84               <&gcc 214>,
85               <&xo_board>;
86      clock-names = "iface",
87                    "ref",
88                    "xo";
89      #clock-cells = <0>;
90      #phy-cells = <0>;
91
92      vddio-supply = <&vreg_l12a_1p8>;
93      vcca-supply = <&vreg_l28a_0p925>;
94    };
95