1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QMP PHY controller (USB, SC8280XP) 8 9maintainers: 10 - Vinod Koul <vkoul@kernel.org> 11 12description: 13 The QMP PHY controller supports physical layer functionality for a number of 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 16properties: 17 compatible: 18 enum: 19 - qcom,ipq9574-qmp-usb3-phy 20 - qcom,sa8775p-qmp-usb3-uni-phy 21 - qcom,sc8280xp-qmp-usb3-uni-phy 22 23 reg: 24 maxItems: 1 25 26 clocks: 27 maxItems: 4 28 29 clock-names: 30 maxItems: 4 31 32 power-domains: 33 maxItems: 1 34 35 resets: 36 maxItems: 2 37 38 reset-names: 39 items: 40 - const: phy 41 - const: phy_phy 42 43 vdda-phy-supply: true 44 45 vdda-pll-supply: true 46 47 "#clock-cells": 48 const: 0 49 50 clock-output-names: 51 maxItems: 1 52 53 "#phy-cells": 54 const: 0 55 56required: 57 - compatible 58 - reg 59 - clocks 60 - clock-names 61 - resets 62 - reset-names 63 - vdda-phy-supply 64 - vdda-pll-supply 65 - "#clock-cells" 66 - clock-output-names 67 - "#phy-cells" 68 69allOf: 70 - if: 71 properties: 72 compatible: 73 contains: 74 enum: 75 - qcom,ipq9574-qmp-usb3-phy 76 then: 77 properties: 78 clock-names: 79 items: 80 - const: aux 81 - const: ref 82 - const: cfg_ahb 83 - const: pipe 84 85 - if: 86 properties: 87 compatible: 88 contains: 89 enum: 90 - qcom,sa8775p-qmp-usb3-uni-phy 91 - qcom,sc8280xp-qmp-usb3-uni-phy 92 then: 93 properties: 94 clocks: 95 maxItems: 4 96 clock-names: 97 items: 98 - const: aux 99 - const: ref 100 - const: com_aux 101 - const: pipe 102 required: 103 - power-domains 104 105additionalProperties: false 106 107examples: 108 - | 109 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 110 #include <dt-bindings/clock/qcom,rpmh.h> 111 112 phy@88ef000 { 113 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 114 reg = <0x088ef000 0x2000>; 115 116 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 117 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 118 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 119 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 120 clock-names = "aux", "ref", "com_aux", "pipe"; 121 122 power-domains = <&gcc USB30_MP_GDSC>; 123 124 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 125 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 126 reset-names = "phy", "phy_phy"; 127 128 vdda-phy-supply = <&vreg_l3a>; 129 vdda-pll-supply = <&vreg_l5a>; 130 131 #clock-cells = <0>; 132 clock-output-names = "usb2_phy0_pipe_clk"; 133 134 #phy-cells = <0>; 135 }; 136