1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm QMP PHY controller (MSM8996 PCIe) 8 9maintainers: 10 - Vinod Koul <vkoul@kernel.org> 11 12description: 13 QMP PHY controller supports physical layer functionality for a number of 14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. 15 16properties: 17 compatible: 18 const: qcom,msm8996-qmp-pcie-phy 19 20 reg: 21 items: 22 - description: serdes 23 24 "#address-cells": 25 enum: [ 1, 2 ] 26 27 "#size-cells": 28 enum: [ 1, 2 ] 29 30 ranges: true 31 32 clocks: 33 maxItems: 3 34 35 clock-names: 36 items: 37 - const: aux 38 - const: cfg_ahb 39 - const: ref 40 41 resets: 42 maxItems: 3 43 44 reset-names: 45 items: 46 - const: phy 47 - const: common 48 - const: cfg 49 50 vdda-phy-supply: true 51 52 vdda-pll-supply: true 53 54 vddp-ref-clk-supply: true 55 56patternProperties: 57 "^phy@[0-9a-f]+$": 58 type: object 59 description: one child node per PHY provided by this block 60 61required: 62 - compatible 63 - reg 64 - "#address-cells" 65 - "#size-cells" 66 - ranges 67 - clocks 68 - clock-names 69 - resets 70 - reset-names 71 - vdda-phy-supply 72 - vdda-pll-supply 73 74additionalProperties: false 75 76examples: 77 - | 78 #include <dt-bindings/clock/qcom,gcc-msm8996.h> 79 pcie_phy: phy-wrapper@34000 { 80 compatible = "qcom,msm8996-qmp-pcie-phy"; 81 reg = <0x34000 0x488>; 82 #address-cells = <1>; 83 #size-cells = <1>; 84 ranges = <0x0 0x34000 0x4000>; 85 86 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 87 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, 88 <&gcc GCC_PCIE_CLKREF_CLK>; 89 clock-names = "aux", "cfg_ahb", "ref"; 90 91 resets = <&gcc GCC_PCIE_PHY_BCR>, 92 <&gcc GCC_PCIE_PHY_COM_BCR>, 93 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; 94 reset-names = "phy", "common", "cfg"; 95 96 vdda-phy-supply = <&vreg_l28a_0p925>; 97 vdda-pll-supply = <&vreg_l12a_1p8>; 98 99 pciephy_0: phy@1000 { 100 reg = <0x1000 0x130>, 101 <0x1200 0x200>, 102 <0x1400 0x1dc>; 103 104 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 105 clock-names = "pipe0"; 106 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 107 reset-names = "lane0"; 108 109 #clock-cells = <0>; 110 clock-output-names = "pcie_0_pipe_clk_src"; 111 112 #phy-cells = <0>; 113 }; 114 115 pciephy_1: phy@2000 { 116 reg = <0x2000 0x130>, 117 <0x2200 0x200>, 118 <0x2400 0x1dc>; 119 120 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 121 clock-names = "pipe1"; 122 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 123 reset-names = "lane1"; 124 125 #clock-cells = <0>; 126 clock-output-names = "pcie_1_pipe_clk_src"; 127 128 #phy-cells = <0>; 129 }; 130 131 pciephy_2: phy@3000 { 132 reg = <0x3000 0x130>, 133 <0x3200 0x200>, 134 <0x3400 0x1dc>; 135 136 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 137 clock-names = "pipe2"; 138 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 139 reset-names = "lane2"; 140 141 #clock-cells = <0>; 142 clock-output-names = "pcie_2_pipe_clk_src"; 143 144 #phy-cells = <0>; 145 }; 146 }; 147