1*2f14bc38SDmitry Baryshkov# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*2f14bc38SDmitry Baryshkov%YAML 1.2
3*2f14bc38SDmitry Baryshkov---
4*2f14bc38SDmitry Baryshkov
5*2f14bc38SDmitry Baryshkov$id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-qmp.yaml#
6*2f14bc38SDmitry Baryshkov$schema: http://devicetree.org/meta-schemas/core.yaml#
7*2f14bc38SDmitry Baryshkov
8*2f14bc38SDmitry Baryshkovtitle: Qualcomm Adreno/Snapdragon QMP HDMI phy
9*2f14bc38SDmitry Baryshkov
10*2f14bc38SDmitry Baryshkovmaintainers:
11*2f14bc38SDmitry Baryshkov  - Rob Clark <robdclark@gmail.com>
12*2f14bc38SDmitry Baryshkov
13*2f14bc38SDmitry Baryshkovproperties:
14*2f14bc38SDmitry Baryshkov  compatible:
15*2f14bc38SDmitry Baryshkov    enum:
16*2f14bc38SDmitry Baryshkov      - qcom,hdmi-phy-8996
17*2f14bc38SDmitry Baryshkov
18*2f14bc38SDmitry Baryshkov  reg:
19*2f14bc38SDmitry Baryshkov    maxItems: 6
20*2f14bc38SDmitry Baryshkov
21*2f14bc38SDmitry Baryshkov  reg-names:
22*2f14bc38SDmitry Baryshkov    items:
23*2f14bc38SDmitry Baryshkov      - const: hdmi_pll
24*2f14bc38SDmitry Baryshkov      - const: hdmi_tx_l0
25*2f14bc38SDmitry Baryshkov      - const: hdmi_tx_l1
26*2f14bc38SDmitry Baryshkov      - const: hdmi_tx_l2
27*2f14bc38SDmitry Baryshkov      - const: hdmi_tx_l3
28*2f14bc38SDmitry Baryshkov      - const: hdmi_phy
29*2f14bc38SDmitry Baryshkov
30*2f14bc38SDmitry Baryshkov  clocks:
31*2f14bc38SDmitry Baryshkov    maxItems: 2
32*2f14bc38SDmitry Baryshkov
33*2f14bc38SDmitry Baryshkov  clock-names:
34*2f14bc38SDmitry Baryshkov    items:
35*2f14bc38SDmitry Baryshkov      - const: iface
36*2f14bc38SDmitry Baryshkov      - const: ref
37*2f14bc38SDmitry Baryshkov
38*2f14bc38SDmitry Baryshkov  power-domains:
39*2f14bc38SDmitry Baryshkov    maxItems: 1
40*2f14bc38SDmitry Baryshkov
41*2f14bc38SDmitry Baryshkov  vcca-supply:
42*2f14bc38SDmitry Baryshkov    description: phandle to VCCA supply regulator
43*2f14bc38SDmitry Baryshkov
44*2f14bc38SDmitry Baryshkov  vddio-supply:
45*2f14bc38SDmitry Baryshkov    description: phandle to VDD I/O supply regulator
46*2f14bc38SDmitry Baryshkov
47*2f14bc38SDmitry Baryshkov  '#phy-cells':
48*2f14bc38SDmitry Baryshkov    const: 0
49*2f14bc38SDmitry Baryshkov
50*2f14bc38SDmitry Baryshkovrequired:
51*2f14bc38SDmitry Baryshkov  - compatible
52*2f14bc38SDmitry Baryshkov  - clocks
53*2f14bc38SDmitry Baryshkov  - clock-names
54*2f14bc38SDmitry Baryshkov  - reg
55*2f14bc38SDmitry Baryshkov  - reg-names
56*2f14bc38SDmitry Baryshkov  - '#phy-cells'
57*2f14bc38SDmitry Baryshkov
58*2f14bc38SDmitry BaryshkovadditionalProperties: false
59*2f14bc38SDmitry Baryshkov
60*2f14bc38SDmitry Baryshkovexamples:
61*2f14bc38SDmitry Baryshkov  - |
62*2f14bc38SDmitry Baryshkov    hdmi-phy@9a0600 {
63*2f14bc38SDmitry Baryshkov      compatible = "qcom,hdmi-phy-8996";
64*2f14bc38SDmitry Baryshkov      reg = <0x009a0600 0x1c4>,
65*2f14bc38SDmitry Baryshkov            <0x009a0a00 0x124>,
66*2f14bc38SDmitry Baryshkov            <0x009a0c00 0x124>,
67*2f14bc38SDmitry Baryshkov            <0x009a0e00 0x124>,
68*2f14bc38SDmitry Baryshkov            <0x009a1000 0x124>,
69*2f14bc38SDmitry Baryshkov            <0x009a1200 0x0c8>;
70*2f14bc38SDmitry Baryshkov      reg-names = "hdmi_pll",
71*2f14bc38SDmitry Baryshkov                  "hdmi_tx_l0",
72*2f14bc38SDmitry Baryshkov                  "hdmi_tx_l1",
73*2f14bc38SDmitry Baryshkov                  "hdmi_tx_l2",
74*2f14bc38SDmitry Baryshkov                  "hdmi_tx_l3",
75*2f14bc38SDmitry Baryshkov                  "hdmi_phy";
76*2f14bc38SDmitry Baryshkov
77*2f14bc38SDmitry Baryshkov      clocks = <&mmcc 116>,
78*2f14bc38SDmitry Baryshkov               <&gcc 214>;
79*2f14bc38SDmitry Baryshkov      clock-names = "iface",
80*2f14bc38SDmitry Baryshkov                    "ref";
81*2f14bc38SDmitry Baryshkov      #phy-cells = <0>;
82*2f14bc38SDmitry Baryshkov
83*2f14bc38SDmitry Baryshkov      vddio-supply = <&vreg_l12a_1p8>;
84*2f14bc38SDmitry Baryshkov      vcca-supply = <&vreg_l28a_0p925>;
85*2f14bc38SDmitry Baryshkov    };
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