15c2ecfceSDavid Heidelberg# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
25c2ecfceSDavid Heidelberg%YAML 1.2
35c2ecfceSDavid Heidelberg---
45c2ecfceSDavid Heidelberg$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
55c2ecfceSDavid Heidelberg$schema: "http://devicetree.org/meta-schemas/core.yaml#"
65c2ecfceSDavid Heidelberg
7*93134b0aSVidya Sagartitle: NVIDIA Tegra194 & Tegra234 P2U binding
85c2ecfceSDavid Heidelberg
95c2ecfceSDavid Heidelbergmaintainers:
105c2ecfceSDavid Heidelberg  - Thierry Reding <treding@nvidia.com>
115c2ecfceSDavid Heidelberg
125c2ecfceSDavid Heidelbergdescription: >
135c2ecfceSDavid Heidelberg  Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
145c2ecfceSDavid Heidelberg  Speed) each interfacing with 12 and 8 P2U instances respectively.
15*93134b0aSVidya Sagar  Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
16*93134b0aSVidya Sagar  each interfacing with 8, 8 and 8 P2U instances respectively.
175c2ecfceSDavid Heidelberg  A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
18*93134b0aSVidya Sagar  interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
19*93134b0aSVidya Sagar  PCIe lane.
205c2ecfceSDavid Heidelberg
215c2ecfceSDavid Heidelbergproperties:
225c2ecfceSDavid Heidelberg  compatible:
23*93134b0aSVidya Sagar    enum:
24*93134b0aSVidya Sagar      - nvidia,tegra194-p2u
25*93134b0aSVidya Sagar      - nvidia,tegra234-p2u
265c2ecfceSDavid Heidelberg
275c2ecfceSDavid Heidelberg  reg:
285c2ecfceSDavid Heidelberg    maxItems: 1
295c2ecfceSDavid Heidelberg    description: Should be the physical address space and length of respective each P2U instance.
305c2ecfceSDavid Heidelberg
315c2ecfceSDavid Heidelberg  reg-names:
325c2ecfceSDavid Heidelberg    items:
335c2ecfceSDavid Heidelberg      - const: ctl
345c2ecfceSDavid Heidelberg
35*93134b0aSVidya Sagar  nvidia,skip-sz-protect-en:
36*93134b0aSVidya Sagar    description: Should be present if two PCIe retimers are present between
37*93134b0aSVidya Sagar      the root port and its immediate downstream device.
38*93134b0aSVidya Sagar    type: boolean
39*93134b0aSVidya Sagar
405c2ecfceSDavid Heidelberg  '#phy-cells':
415c2ecfceSDavid Heidelberg    const: 0
425c2ecfceSDavid Heidelberg
435c2ecfceSDavid HeidelbergadditionalProperties: false
445c2ecfceSDavid Heidelberg
455c2ecfceSDavid Heidelbergexamples:
465c2ecfceSDavid Heidelberg  - |
475c2ecfceSDavid Heidelberg    p2u_hsio_0: phy@3e10000 {
485c2ecfceSDavid Heidelberg        compatible = "nvidia,tegra194-p2u";
495c2ecfceSDavid Heidelberg        reg = <0x03e10000 0x10000>;
505c2ecfceSDavid Heidelberg        reg-names = "ctl";
515c2ecfceSDavid Heidelberg
525c2ecfceSDavid Heidelberg        #phy-cells = <0>;
535c2ecfceSDavid Heidelberg    };
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