1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: STMicroelectronics STM32 USB HS PHY controller binding 8 9description: 10 11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI 12 switch. It controls PHY configuration and status, and the UTMI+ switch that 13 selects either OTG or HOST controller for the second PHY port. It also sets 14 PLL configuration. 15 16 USBPHYC 17 |_ PLL 18 | 19 |_ PHY port#1 _________________ HOST controller 20 | __ | 21 | / 1|________________| 22 |_ PHY port#2 ----| |________________ 23 | \_0| | 24 |_ UTMI switch_______| OTG controller 25 26maintainers: 27 - Amelie Delaunay <amelie.delaunay@foss.st.com> 28 29properties: 30 compatible: 31 const: st,stm32mp1-usbphyc 32 33 reg: 34 maxItems: 1 35 36 clocks: 37 maxItems: 1 38 39 resets: 40 maxItems: 1 41 42 "#address-cells": 43 const: 1 44 45 "#size-cells": 46 const: 0 47 48 vdda1v1-supply: 49 description: regulator providing 1V1 power supply to the PLL block 50 51 vdda1v8-supply: 52 description: regulator providing 1V8 power supply to the PLL block 53 54 '#clock-cells': 55 description: number of clock cells for ck_usbo_48m consumer 56 const: 0 57 58#Required child nodes: 59 60patternProperties: 61 "^usb-phy@[0|1]$": 62 type: object 63 description: 64 Each port the controller provides must be represented as a sub-node. 65 66 properties: 67 reg: 68 description: phy port index. 69 maxItems: 1 70 71 phy-supply: 72 description: regulator providing 3V3 power supply to the PHY. 73 74 "#phy-cells": 75 enum: [ 0x0, 0x1 ] 76 77 connector: 78 type: object 79 $ref: /schemas/connector/usb-connector.yaml 80 unevaluatedProperties: false 81 82 properties: 83 vbus-supply: true 84 85 # It can be necessary to adjust the PHY settings to compensate parasitics, which can be due 86 # to USB connector/receptacle, routing, ESD protection component,... Here is the list of 87 # all optional parameters to tune the interface of the PHY (HS for High-Speed, FS for Full- 88 # Speed, LS for Low-Speed) 89 90 st,current-boost-microamp: 91 description: Current boosting in uA 92 enum: [ 1000, 2000 ] 93 94 st,no-lsfs-fb-cap: 95 description: Disables the LS/FS feedback capacitor 96 type: boolean 97 98 st,decrease-hs-slew-rate: 99 description: Decreases the HS driver slew rate by 10% 100 type: boolean 101 102 st,tune-hs-dc-level: 103 description: | 104 Tunes the HS driver DC level 105 - <0> normal level 106 - <1> increases the level by 5 to 7 mV 107 - <2> increases the level by 10 to 14 mV 108 - <3> decreases the level by 5 to 7 mV 109 $ref: /schemas/types.yaml#/definitions/uint32 110 minimum: 0 111 maximum: 3 112 default: 0 113 114 st,enable-fs-rftime-tuning: 115 description: Enables the FS rise/fall tuning option 116 type: boolean 117 118 st,enable-hs-rftime-reduction: 119 description: Enables the HS rise/fall reduction feature 120 type: boolean 121 122 st,trim-hs-current: 123 description: | 124 Controls HS driver current trimming for choke compensation 125 - <0> = 18.87 mA target current / nominal + 0% 126 - <1> = 19.165 mA target current / nominal + 1.56% 127 - <2> = 19.46 mA target current / nominal + 3.12% 128 - <3> = 19.755 mA target current / nominal + 4.68% 129 - <4> = 20.05 mA target current / nominal + 6.24% 130 - <5> = 20.345 mA target current / nominal + 7.8% 131 - <6> = 20.64 mA target current / nominal + 9.36% 132 - <7> = 20.935 mA target current / nominal + 10.92% 133 - <8> = 21.23 mA target current / nominal + 12.48% 134 - <9> = 21.525 mA target current / nominal + 14.04% 135 - <10> = 21.82 mA target current / nominal + 15.6% 136 - <11> = 22.115 mA target current / nominal + 17.16% 137 - <12> = 22.458 mA target current / nominal + 19.01% 138 - <13> = 22.755 mA target current / nominal + 20.58% 139 - <14> = 23.052 mA target current / nominal + 22.16% 140 - <15> = 23.348 mA target current / nominal + 23.73% 141 $ref: /schemas/types.yaml#/definitions/uint32 142 minimum: 0 143 maximum: 15 144 default: 0 145 146 st,trim-hs-impedance: 147 description: | 148 Controls HS driver impedance tuning for choke compensation 149 - <0> = no impedance offset 150 - <1> = reduce the impedance by 2 ohms 151 - <2> = reduce the impedance by 4 ohms 152 - <3> = reduce the impedance by 6 ohms 153 $ref: /schemas/types.yaml#/definitions/uint32 154 minimum: 0 155 maximum: 3 156 default: 0 157 158 st,tune-squelch-level: 159 description: | 160 Tunes the squelch DC threshold value 161 - <0> = no shift in threshold 162 - <1> = threshold shift by +7 mV 163 - <2> = threshold shift by -5 mV 164 - <3> = threshold shift by +14 mV 165 $ref: /schemas/types.yaml#/definitions/uint32 166 minimum: 0 167 maximum: 3 168 default: 0 169 170 st,enable-hs-rx-gain-eq: 171 description: Enables the HS Rx gain equalizer 172 type: boolean 173 174 st,tune-hs-rx-offset: 175 description: | 176 Adjusts the HS Rx offset 177 - <0> = no offset 178 - <1> = offset of +5 mV 179 - <2> = offset of +10 mV 180 - <3> = offset of -5 mV 181 $ref: /schemas/types.yaml#/definitions/uint32 182 minimum: 0 183 maximum: 3 184 default: 0 185 186 st,no-hs-ftime-ctrl: 187 description: Disables the HS fall time control of single ended signals during pre-emphasis 188 type: boolean 189 190 st,no-lsfs-sc: 191 description: Disables the short circuit protection in LS/FS driver 192 type: boolean 193 194 st,enable-hs-tx-staggering: 195 description: Enables the basic staggering in HS Tx mode 196 type: boolean 197 198 allOf: 199 - if: 200 properties: 201 reg: 202 const: 0 203 then: 204 properties: 205 "#phy-cells": 206 const: 0 207 else: 208 properties: 209 "#phy-cells": 210 const: 1 211 description: 212 The value is used to select UTMI switch output. 213 0 for OTG controller and 1 for Host controller. 214 215 required: 216 - reg 217 - phy-supply 218 - "#phy-cells" 219 220 additionalProperties: false 221 222required: 223 - compatible 224 - reg 225 - clocks 226 - "#address-cells" 227 - "#size-cells" 228 - vdda1v1-supply 229 - vdda1v8-supply 230 - usb-phy@0 231 - usb-phy@1 232 233additionalProperties: false 234 235examples: 236 - | 237 #include <dt-bindings/clock/stm32mp1-clks.h> 238 #include <dt-bindings/reset/stm32mp1-resets.h> 239 usbphyc: usbphyc@5a006000 { 240 compatible = "st,stm32mp1-usbphyc"; 241 reg = <0x5a006000 0x1000>; 242 clocks = <&rcc USBPHY_K>; 243 resets = <&rcc USBPHY_R>; 244 vdda1v1-supply = <®11>; 245 vdda1v8-supply = <®18>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 #clock-cells = <0>; 249 250 usbphyc_port0: usb-phy@0 { 251 reg = <0>; 252 phy-supply = <&vdd_usb>; 253 #phy-cells = <0>; 254 st,tune-hs-dc-level = <2>; 255 st,enable-fs-rftime-tuning; 256 st,enable-hs-rftime-reduction; 257 st,trim-hs-current = <15>; 258 st,trim-hs-impedance = <1>; 259 st,tune-squelch-level = <3>; 260 st,tune-hs-rx-offset = <2>; 261 st,no-lsfs-sc; 262 connector { 263 compatible = "usb-a-connector"; 264 vbus-supply = <&vbus_sw>; 265 }; 266 }; 267 268 usbphyc_port1: usb-phy@1 { 269 reg = <1>; 270 phy-supply = <&vdd_usb>; 271 #phy-cells = <1>; 272 st,tune-hs-dc-level = <2>; 273 st,enable-fs-rftime-tuning; 274 st,enable-hs-rftime-reduction; 275 st,trim-hs-current = <15>; 276 st,trim-hs-impedance = <1>; 277 st,tune-squelch-level = <3>; 278 st,tune-hs-rx-offset = <2>; 279 st,no-lsfs-sc; 280 }; 281 }; 282... 283