1MVEBU comphy drivers 2-------------------- 3 4COMPHY controllers can be found on the following Marvell MVEBU SoCs: 5* Armada 7k/8k (on the CP110) 6* Armada 3700 7It provides a number of shared PHYs used by various interfaces (network, SATA, 8USB, PCIe...). 9 10Required properties: 11 12- compatible: should be one of: 13 * "marvell,comphy-cp110" for Armada 7k/8k 14 * "marvell,comphy-a3700" for Armada 3700 15- reg: should contain the COMPHY register(s) location(s) and length(s). 16 * 1 entry for Armada 7k/8k 17 * 4 entries for Armada 3700 along with the corresponding reg-names 18 properties, memory areas are: 19 * Generic COMPHY registers 20 * Lane 1 (PCIe/GbE) 21 * Lane 0 (USB3/GbE) 22 * Lane 2 (SATA/USB3) 23- marvell,system-controller: should contain a phandle to the system 24 controller node (only for Armada 7k/8k) 25- #address-cells: should be 1. 26- #size-cells: should be 0. 27 28A sub-node is required for each comphy lane provided by the comphy. 29 30Required properties (child nodes): 31 32- reg: COMPHY lane number. 33- #phy-cells : from the generic PHY bindings, must be 1. Defines the 34 input port to use for a given comphy lane. 35 36Examples: 37 38 cpm_comphy: phy@120000 { 39 compatible = "marvell,comphy-cp110"; 40 reg = <0x120000 0x6000>; 41 marvell,system-controller = <&cpm_syscon0>; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 45 cpm_comphy0: phy@0 { 46 reg = <0>; 47 #phy-cells = <1>; 48 }; 49 50 cpm_comphy1: phy@1 { 51 reg = <1>; 52 #phy-cells = <1>; 53 }; 54 }; 55 56 comphy: phy@18300 { 57 compatible = "marvell,comphy-a3700"; 58 reg = <0x18300 0x300>, 59 <0x1F000 0x400>, 60 <0x5C000 0x400>, 61 <0xe0178 0x8>; 62 reg-names = "comphy", 63 "lane1_pcie_gbe", 64 "lane0_usb3_gbe", 65 "lane2_sata_usb3"; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 69 70 comphy0: phy@0 { 71 reg = <0>; 72 #phy-cells = <1>; 73 }; 74 75 comphy1: phy@1 { 76 reg = <1>; 77 #phy-cells = <1>; 78 }; 79 80 comphy2: phy@2 { 81 reg = <2>; 82 #phy-cells = <1>; 83 }; 84 }; 85