1STMicroelectronics STi MIPHY28LP PHY binding
2============================================
3
4This binding describes a miphy device that is used to control PHY hardware
5for SATA, PCIe or USB3.
6
7Required properties (controller (parent) node):
8- compatible	: Should be "st,miphy28lp-phy".
9- st,syscfg	: Should be a phandle of the system configuration register group
10		  which contain the SATA, PCIe or USB3 mode setting bits.
11
12Required nodes	:  A sub-node is required for each channel the controller
13		   provides. Address range information including the usual
14		   'reg' and 'reg-names' properties are used inside these
15		   nodes to describe the controller's topology. These nodes
16		   are translated by the driver's .xlate() function.
17
18Required properties (port (child) node):
19- #phy-cells	: Should be 1 (See second example)
20		  Cell after port phandle is device type from:
21			- PHY_TYPE_SATA
22			- PHY_TYPE_PCI
23			- PHY_TYPE_USB3
24- reg		: Address and length of the register set for the device.
25- reg-names	: The names of the register addresses corresponding to the registers
26		  filled in "reg". It can also contain the offset of the system configuration
27		  registers used as glue-logic to setup the device for SATA/PCIe or USB3
28		  devices.
29- resets	: phandle to the parent reset controller.
30- reset-names	: Associated name must be "miphy-sw-rst".
31
32Optional properties (port (child) node):
33- st,osc-rdy		: to check the MIPHY0_OSC_RDY status in the glue-logic. This
34			  is not available in all the MiPHY. For example, for STiH407, only the
35			  MiPHY0 has this bit.
36- st,osc-force-ext	: to select the external oscillator. This can change from
37			  different MiPHY inside the same SoC.
38- st,sata_gen		: to select which SATA_SPDMODE has to be set in the SATA system config
39			  register.
40- st,px_rx_pol_inv	: to invert polarity of RXn/RXp (respectively negative line and positive
41			  line).
42
43example:
44
45		miphy28lp_phy: miphy28lp@9b22000 {
46			compatible = "st,miphy28lp-phy";
47			st,syscfg = <&syscfg_core>;
48			#address-cells	= <1>;
49			#size-cells	= <1>;
50			ranges;
51
52			phy_port0: port@9b22000 {
53				reg = <0x9b22000 0xff>,
54				      <0x9b09000 0xff>,
55				      <0x9b04000 0xff>,
56				      <0x114 0x4>, /* sysctrl MiPHY cntrl */
57				      <0x818 0x4>, /* sysctrl MiPHY status*/
58				      <0xe0  0x4>, /* sysctrl PCIe */
59				      <0xec  0x4>; /* sysctrl SATA */
60				reg-names = "sata-up",
61					    "pcie-up",
62					    "pipew",
63					    "miphy-ctrl-glue",
64					    "miphy-status-glue",
65					    "pcie-glue",
66					    "sata-glue";
67				#phy-cells = <1>;
68				st,osc-rdy;
69				reset-names = "miphy-sw-rst";
70				resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
71			};
72
73			phy_port1: port@9b2a000 {
74				reg = <0x9b2a000 0xff>,
75				      <0x9b19000 0xff>,
76				      <0x9b14000 0xff>,
77				      <0x118 0x4>,
78				      <0x81c 0x4>,
79				      <0xe4  0x4>,
80				      <0xf0  0x4>;
81				reg-names = "sata-up",
82					    "pcie-up",
83					    "pipew",
84					    "miphy-ctrl-glue",
85					    "miphy-status-glue",
86					    "pcie-glue",
87					    "sata-glue";
88				#phy-cells = <1>;
89				st,osc-force-ext;
90				reset-names = "miphy-sw-rst";
91				resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
92			};
93
94			phy_port2: port@8f95000 {
95				reg = <0x8f95000 0xff>,
96				      <0x8f90000 0xff>,
97				      <0x11c 0x4>,
98				      <0x820 0x4>;
99				reg-names = "pipew",
100				    "usb3-up",
101				    "miphy-ctrl-glue",
102				    "miphy-status-glue";
103				#phy-cells = <1>;
104				reset-names = "miphy-sw-rst";
105				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
106			};
107		};
108
109
110Specifying phy control of devices
111=================================
112
113Device nodes should specify the configuration required in their "phys"
114property, containing a phandle to the miphy device node and an index
115specifying which configuration to use, as described in phy-bindings.txt.
116
117example:
118		sata0: sata@9b20000  {
119			...
120			phys		= <&phy_port0 PHY_TYPE_SATA>;
121			...
122		};
123
124Macro definitions for the supported miphy configuration can be found in:
125
126include/dt-bindings/phy/phy-miphy28lp.h
127