1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: Cadence Sierra PHY binding
8
9description:
10  This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
11  multiprotocol combinations including protocols such as PCIe, USB etc.
12
13maintainers:
14  - Swapnil Jakhade <sjakhade@cadence.com>
15  - Yuti Amonkar <yamonkar@cadence.com>
16
17properties:
18  compatible:
19    enum:
20      - cdns,sierra-phy-t0
21      - ti,sierra-phy-t0
22
23  '#address-cells':
24    const: 1
25
26  '#size-cells':
27    const: 0
28
29  resets:
30    minItems: 1
31    maxItems: 2
32    items:
33      - description: Sierra PHY reset.
34      - description: Sierra APB reset. This is optional.
35
36  reset-names:
37    minItems: 1
38    maxItems: 2
39    items:
40      - const: sierra_reset
41      - const: sierra_apb
42
43  reg:
44    maxItems: 1
45    description:
46      Offset of the Sierra PHY configuration registers.
47
48  reg-names:
49    const: serdes
50
51  clocks:
52    maxItems: 2
53
54  clock-names:
55    items:
56      - const: cmn_refclk_dig_div
57      - const: cmn_refclk1_dig_div
58
59  cdns,autoconf:
60    type: boolean
61    description:
62      A boolean property whose presence indicates that the PHY registers will be
63      configured by hardware. If not present, all sub-node optional properties
64      must be provided.
65
66patternProperties:
67  '^phy@[0-9a-f]$':
68    type: object
69    description:
70      Each group of PHY lanes with a single master lane should be represented as
71      a sub-node. Note that the actual configuration of each lane is determined
72      by hardware strapping, and must match the configuration specified here.
73    properties:
74      reg:
75        description:
76          The master lane number. This is the lowest numbered lane in the lane group.
77        minimum: 0
78        maximum: 15
79
80      resets:
81        minItems: 1
82        maxItems: 4
83        description:
84          Contains list of resets, one per lane, to get all the link lanes out of reset.
85
86      "#phy-cells":
87        const: 0
88
89      cdns,phy-type:
90        description:
91          Specifies the type of PHY for which the group of PHY lanes is used.
92          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
93        $ref: /schemas/types.yaml#/definitions/uint32
94        enum: [2, 4]
95
96      cdns,num-lanes:
97        description:
98          Number of lanes in this group. The group is made up of consecutive lanes.
99        $ref: /schemas/types.yaml#/definitions/uint32
100        minimum: 1
101        maximum: 16
102
103    required:
104      - reg
105      - resets
106      - "#phy-cells"
107
108    additionalProperties: false
109
110required:
111  - compatible
112  - "#address-cells"
113  - "#size-cells"
114  - reg
115  - resets
116  - reset-names
117
118additionalProperties: false
119
120examples:
121  - |
122    #include <dt-bindings/phy/phy.h>
123
124    bus {
125        #address-cells = <2>;
126        #size-cells = <2>;
127
128        sierra-phy@fd240000 {
129            compatible = "cdns,sierra-phy-t0";
130            reg = <0x0 0xfd240000 0x0 0x40000>;
131            resets = <&phyrst 0>, <&phyrst 1>;
132            reset-names = "sierra_reset", "sierra_apb";
133            clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
134            clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
135            #address-cells = <1>;
136            #size-cells = <0>;
137            pcie0_phy0: phy@0 {
138                reg = <0>;
139                resets = <&phyrst 2>;
140                cdns,num-lanes = <2>;
141                #phy-cells = <0>;
142                cdns,phy-type = <PHY_TYPE_PCIE>;
143            };
144            pcie0_phy1: phy@2 {
145                reg = <2>;
146                resets = <&phyrst 4>;
147                cdns,num-lanes = <1>;
148                #phy-cells = <0>;
149                cdns,phy-type = <PHY_TYPE_PCIE>;
150            };
151        };
152    };
153