1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek T-PHY Controller Device Tree Bindings
9
10maintainers:
11  - Chunfeng Yun <chunfeng.yun@mediatek.com>
12
13description: |
14  The T-PHY controller supports physical layer functionality for a number of
15  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
16
17  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18  T-PHY V2 (mt2712) when works on USB mode:
19  -----------------------------------
20  Version 1:
21  port        offset    bank
22  shared      0x0000    SPLLC
23              0x0100    FMREG
24  u2 port0    0x0800    U2PHY_COM
25  u3 port0    0x0900    U3PHYD
26              0x0a00    U3PHYD_BANK2
27              0x0b00    U3PHYA
28              0x0c00    U3PHYA_DA
29  u2 port1    0x1000    U2PHY_COM
30  u3 port1    0x1100    U3PHYD
31              0x1200    U3PHYD_BANK2
32              0x1300    U3PHYA
33              0x1400    U3PHYA_DA
34  u2 port2    0x1800    U2PHY_COM
35              ...
36
37  Version 2:
38  port        offset    bank
39  u2 port0    0x0000    MISC
40              0x0100    FMREG
41              0x0300    U2PHY_COM
42  u3 port0    0x0700    SPLLC
43              0x0800    CHIP
44              0x0900    U3PHYD
45              0x0a00    U3PHYD_BANK2
46              0x0b00    U3PHYA
47              0x0c00    U3PHYA_DA
48  u2 port1    0x1000    MISC
49              0x1100    FMREG
50              0x1300    U2PHY_COM
51  u3 port1    0x1700    SPLLC
52              0x1800    CHIP
53              0x1900    U3PHYD
54              0x1a00    U3PHYD_BANK2
55              0x1b00    U3PHYA
56              0x1c00    U3PHYA_DA
57  u2 port2    0x2000    MISC
58              ...
59
60  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
62  added on V2.
63
64properties:
65  $nodename:
66    pattern: "^t-phy@[0-9a-f]+$"
67
68  compatible:
69    oneOf:
70      - items:
71          - enum:
72              - mediatek,mt2701-tphy
73              - mediatek,mt7623-tphy
74              - mediatek,mt7622-tphy
75              - mediatek,mt8516-tphy
76          - const: mediatek,generic-tphy-v1
77      - items:
78          - enum:
79              - mediatek,mt2712-tphy
80              - mediatek,mt7629-tphy
81              - mediatek,mt8183-tphy
82              - mediatek,mt8195-tphy
83          - const: mediatek,generic-tphy-v2
84      - const: mediatek,mt2701-u3phy
85        deprecated: true
86      - const: mediatek,mt2712-u3phy
87        deprecated: true
88      - const: mediatek,mt8173-u3phy
89
90  reg:
91    description:
92      Register shared by multiple ports, exclude port's private register.
93      It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
94      T-PHY V2, such as mt2712.
95    maxItems: 1
96
97  "#address-cells":
98    enum: [1, 2]
99
100  "#size-cells":
101    enum: [1, 2]
102
103  # Used with non-empty value if optional 'reg' is not provided.
104  # The format of the value is an arbitrary number of triplets of
105  # (child-bus-address, parent-bus-address, length).
106  ranges: true
107
108  mediatek,src-ref-clk-mhz:
109    description:
110      Frequency of reference clock for slew rate calibrate
111    default: 26
112
113  mediatek,src-coef:
114    description:
115      Coefficient for slew rate calibrate, depends on SoC process
116    $ref: /schemas/types.yaml#/definitions/uint32
117    default: 28
118
119# Required child node:
120patternProperties:
121  "^(usb|pcie|sata)-phy@[0-9a-f]+$":
122    type: object
123    description:
124      A sub-node is required for each port the controller provides.
125      Address range information including the usual 'reg' property
126      is used inside these nodes to describe the controller's topology.
127
128    properties:
129      reg:
130        maxItems: 1
131
132      clocks:
133        minItems: 1
134        items:
135          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
136          - description: Reference clock of analog phy
137        description:
138          Uses both clocks if the clock of analog and digital phys are
139          separated, otherwise uses "ref" clock only if needed.
140
141      clock-names:
142        minItems: 1
143        items:
144          - const: ref
145          - const: da_ref
146
147      "#phy-cells":
148        const: 1
149        description: |
150          The cells contain the following arguments.
151
152          - description: The PHY type
153              enum:
154                - PHY_TYPE_USB2
155                - PHY_TYPE_USB3
156                - PHY_TYPE_PCIE
157                - PHY_TYPE_SATA
158
159      # The following optional vendor properties are only for debug or HQA test
160      mediatek,eye-src:
161        description:
162          The value of slew rate calibrate (U2 phy)
163        $ref: /schemas/types.yaml#/definitions/uint32
164        minimum: 1
165        maximum: 7
166
167      mediatek,eye-vrt:
168        description:
169          The selection of VRT reference voltage (U2 phy)
170        $ref: /schemas/types.yaml#/definitions/uint32
171        minimum: 1
172        maximum: 7
173
174      mediatek,eye-term:
175        description:
176          The selection of HS_TX TERM reference voltage (U2 phy)
177        $ref: /schemas/types.yaml#/definitions/uint32
178        minimum: 1
179        maximum: 7
180
181      mediatek,intr:
182        description:
183          The selection of internal resistor (U2 phy)
184        $ref: /schemas/types.yaml#/definitions/uint32
185        minimum: 1
186        maximum: 31
187
188      mediatek,discth:
189        description:
190          The selection of disconnect threshold (U2 phy)
191        $ref: /schemas/types.yaml#/definitions/uint32
192        minimum: 1
193        maximum: 15
194
195      mediatek,bc12:
196        description:
197          Specify the flag to enable BC1.2 if support it
198        type: boolean
199
200    required:
201      - reg
202      - "#phy-cells"
203
204    additionalProperties: false
205
206required:
207  - compatible
208  - "#address-cells"
209  - "#size-cells"
210  - ranges
211
212additionalProperties: false
213
214examples:
215  - |
216    #include <dt-bindings/clock/mt8173-clk.h>
217    #include <dt-bindings/interrupt-controller/arm-gic.h>
218    #include <dt-bindings/interrupt-controller/irq.h>
219    #include <dt-bindings/phy/phy.h>
220    usb@11271000 {
221        compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
222        reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
223        reg-names = "mac", "ippc";
224        phys = <&u2port0 PHY_TYPE_USB2>,
225               <&u3port0 PHY_TYPE_USB3>,
226               <&u2port1 PHY_TYPE_USB2>;
227        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
228        clocks = <&topckgen CLK_TOP_USB30_SEL>;
229        clock-names = "sys_ck";
230    };
231
232    t-phy@11290000 {
233        compatible = "mediatek,mt8173-u3phy";
234        reg = <0x11290000 0x800>;
235        #address-cells = <1>;
236        #size-cells = <1>;
237        ranges;
238
239        u2port0: usb-phy@11290800 {
240            reg = <0x11290800 0x100>;
241            clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
242            clock-names = "ref", "da_ref";
243            #phy-cells = <1>;
244        };
245
246        u3port0: usb-phy@11290900 {
247            reg = <0x11290900 0x700>;
248            clocks = <&clk26m>;
249            clock-names = "ref";
250            #phy-cells = <1>;
251        };
252
253        u2port1: usb-phy@11291000 {
254            reg = <0x11291000 0x100>;
255            #phy-cells = <1>;
256        };
257    };
258
259...
260