1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek T-PHY Controller Device Tree Bindings
9
10maintainers:
11  - Chunfeng Yun <chunfeng.yun@mediatek.com>
12
13description: |
14  The T-PHY controller supports physical layer functionality for a number of
15  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
16
17  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18  T-PHY V2 (mt2712) when works on USB mode:
19  -----------------------------------
20  Version 1:
21  port        offset    bank
22  shared      0x0000    SPLLC
23              0x0100    FMREG
24  u2 port0    0x0800    U2PHY_COM
25  u3 port0    0x0900    U3PHYD
26              0x0a00    U3PHYD_BANK2
27              0x0b00    U3PHYA
28              0x0c00    U3PHYA_DA
29  u2 port1    0x1000    U2PHY_COM
30  u3 port1    0x1100    U3PHYD
31              0x1200    U3PHYD_BANK2
32              0x1300    U3PHYA
33              0x1400    U3PHYA_DA
34  u2 port2    0x1800    U2PHY_COM
35              ...
36
37  Version 2:
38  port        offset    bank
39  u2 port0    0x0000    MISC
40              0x0100    FMREG
41              0x0300    U2PHY_COM
42  u3 port0    0x0700    SPLLC
43              0x0800    CHIP
44              0x0900    U3PHYD
45              0x0a00    U3PHYD_BANK2
46              0x0b00    U3PHYA
47              0x0c00    U3PHYA_DA
48  u2 port1    0x1000    MISC
49              0x1100    FMREG
50              0x1300    U2PHY_COM
51  u3 port1    0x1700    SPLLC
52              0x1800    CHIP
53              0x1900    U3PHYD
54              0x1a00    U3PHYD_BANK2
55              0x1b00    U3PHYA
56              0x1c00    U3PHYA_DA
57  u2 port2    0x2000    MISC
58              ...
59
60  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
62  added on V2.
63
64properties:
65  $nodename:
66    pattern: "^t-phy@[0-9a-f]+$"
67
68  compatible:
69    oneOf:
70      - items:
71          - enum:
72              - mediatek,mt2701-tphy
73              - mediatek,mt7623-tphy
74              - mediatek,mt7622-tphy
75              - mediatek,mt8516-tphy
76          - const: mediatek,generic-tphy-v1
77      - items:
78          - enum:
79              - mediatek,mt2712-tphy
80              - mediatek,mt7629-tphy
81              - mediatek,mt8183-tphy
82          - const: mediatek,generic-tphy-v2
83      - const: mediatek,mt2701-u3phy
84        deprecated: true
85      - const: mediatek,mt2712-u3phy
86        deprecated: true
87      - const: mediatek,mt8173-u3phy
88
89  reg:
90    description:
91      Register shared by multiple ports, exclude port's private register.
92      It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
93      T-PHY V2, such as mt2712.
94    maxItems: 1
95
96  "#address-cells":
97    enum: [1, 2]
98
99  "#size-cells":
100    enum: [1, 2]
101
102  # Used with non-empty value if optional 'reg' is not provided.
103  # The format of the value is an arbitrary number of triplets of
104  # (child-bus-address, parent-bus-address, length).
105  ranges: true
106
107  mediatek,src-ref-clk-mhz:
108    description:
109      Frequency of reference clock for slew rate calibrate
110    default: 26
111
112  mediatek,src-coef:
113    description:
114      Coefficient for slew rate calibrate, depends on SoC process
115    $ref: /schemas/types.yaml#/definitions/uint32
116    default: 28
117
118# Required child node:
119patternProperties:
120  "^usb-phy@[0-9a-f]+$":
121    type: object
122    description:
123      A sub-node is required for each port the controller provides.
124      Address range information including the usual 'reg' property
125      is used inside these nodes to describe the controller's topology.
126
127    properties:
128      reg:
129        maxItems: 1
130
131      clocks:
132        minItems: 1
133        maxItems: 2
134        items:
135          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
136          - description: Reference clock of analog phy
137        description:
138          Uses both clocks if the clock of analog and digital phys are
139          separated, otherwise uses "ref" clock only if needed.
140
141      clock-names:
142        minItems: 1
143        maxItems: 2
144        items:
145          - const: ref
146          - const: da_ref
147
148      "#phy-cells":
149        const: 1
150        description: |
151          The cells contain the following arguments.
152
153          - description: The PHY type
154              enum:
155                - PHY_TYPE_USB2
156                - PHY_TYPE_USB3
157                - PHY_TYPE_PCIE
158                - PHY_TYPE_SATA
159
160      # The following optional vendor properties are only for debug or HQA test
161      mediatek,eye-src:
162        description:
163          The value of slew rate calibrate (U2 phy)
164        $ref: /schemas/types.yaml#/definitions/uint32
165        minimum: 1
166        maximum: 7
167
168      mediatek,eye-vrt:
169        description:
170          The selection of VRT reference voltage (U2 phy)
171        $ref: /schemas/types.yaml#/definitions/uint32
172        minimum: 1
173        maximum: 7
174
175      mediatek,eye-term:
176        description:
177          The selection of HS_TX TERM reference voltage (U2 phy)
178        $ref: /schemas/types.yaml#/definitions/uint32
179        minimum: 1
180        maximum: 7
181
182      mediatek,intr:
183        description:
184          The selection of internal resistor (U2 phy)
185        $ref: /schemas/types.yaml#/definitions/uint32
186        minimum: 1
187        maximum: 31
188
189      mediatek,discth:
190        description:
191          The selection of disconnect threshold (U2 phy)
192        $ref: /schemas/types.yaml#/definitions/uint32
193        minimum: 1
194        maximum: 15
195
196      mediatek,bc12:
197        description:
198          Specify the flag to enable BC1.2 if support it
199        type: boolean
200
201    required:
202      - reg
203      - "#phy-cells"
204
205    additionalProperties: false
206
207required:
208  - compatible
209  - "#address-cells"
210  - "#size-cells"
211  - ranges
212
213additionalProperties: false
214
215examples:
216  - |
217    #include <dt-bindings/clock/mt8173-clk.h>
218    #include <dt-bindings/interrupt-controller/arm-gic.h>
219    #include <dt-bindings/interrupt-controller/irq.h>
220    #include <dt-bindings/phy/phy.h>
221    usb@11271000 {
222        compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
223        reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
224        reg-names = "mac", "ippc";
225        phys = <&u2port0 PHY_TYPE_USB2>,
226               <&u3port0 PHY_TYPE_USB3>,
227               <&u2port1 PHY_TYPE_USB2>;
228        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
229        clocks = <&topckgen CLK_TOP_USB30_SEL>;
230        clock-names = "sys_ck";
231    };
232
233    t-phy@11290000 {
234        compatible = "mediatek,mt8173-u3phy";
235        reg = <0x11290000 0x800>;
236        #address-cells = <1>;
237        #size-cells = <1>;
238        ranges;
239
240        u2port0: usb-phy@11290800 {
241            reg = <0x11290800 0x100>;
242            clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
243            clock-names = "ref", "da_ref";
244            #phy-cells = <1>;
245        };
246
247        u3port0: usb-phy@11290900 {
248            reg = <0x11290900 0x700>;
249            clocks = <&clk26m>;
250            clock-names = "ref";
251            #phy-cells = <1>;
252        };
253
254        u2port1: usb-phy@11291000 {
255            reg = <0x11291000 0x100>;
256            #phy-cells = <1>;
257        };
258    };
259
260...
261