1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek T-PHY Controller
9
10maintainers:
11  - Chunfeng Yun <chunfeng.yun@mediatek.com>
12
13description: |
14  The T-PHY controller supports physical layer functionality for a number of
15  controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
16
17  Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18  T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19  -----------------------------------
20  Version 1:
21  port        offset    bank
22  shared      0x0000    SPLLC
23              0x0100    FMREG
24  u2 port0    0x0800    U2PHY_COM
25  u3 port0    0x0900    U3PHYD
26              0x0a00    U3PHYD_BANK2
27              0x0b00    U3PHYA
28              0x0c00    U3PHYA_DA
29  u2 port1    0x1000    U2PHY_COM
30  u3 port1    0x1100    U3PHYD
31              0x1200    U3PHYD_BANK2
32              0x1300    U3PHYA
33              0x1400    U3PHYA_DA
34  u2 port2    0x1800    U2PHY_COM
35              ...
36
37  Version 2/3:
38  port        offset    bank
39  u2 port0    0x0000    MISC
40              0x0100    FMREG
41              0x0300    U2PHY_COM
42  u3 port0    0x0700    SPLLC
43              0x0800    CHIP
44              0x0900    U3PHYD
45              0x0a00    U3PHYD_BANK2
46              0x0b00    U3PHYA
47              0x0c00    U3PHYA_DA
48  u2 port1    0x1000    MISC
49              0x1100    FMREG
50              0x1300    U2PHY_COM
51  u3 port1    0x1700    SPLLC
52              0x1800    CHIP
53              0x1900    U3PHYD
54              0x1a00    U3PHYD_BANK2
55              0x1b00    U3PHYA
56              0x1c00    U3PHYA_DA
57  u2 port2    0x2000    MISC
58              ...
59
60  SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61  into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
62  added on V2; the FMREG bank for slew rate calibration is not used anymore
63  and reserved on V3;
64
65properties:
66  $nodename:
67    pattern: "^t-phy(@[0-9a-f]+)?$"
68
69  compatible:
70    oneOf:
71      - items:
72          - enum:
73              - mediatek,mt2701-tphy
74              - mediatek,mt7623-tphy
75              - mediatek,mt7622-tphy
76              - mediatek,mt8516-tphy
77          - const: mediatek,generic-tphy-v1
78      - items:
79          - enum:
80              - mediatek,mt2712-tphy
81              - mediatek,mt7629-tphy
82              - mediatek,mt7986-tphy
83              - mediatek,mt8183-tphy
84              - mediatek,mt8186-tphy
85              - mediatek,mt8192-tphy
86              - mediatek,mt8365-tphy
87          - const: mediatek,generic-tphy-v2
88      - items:
89          - enum:
90              - mediatek,mt8188-tphy
91              - mediatek,mt8195-tphy
92          - const: mediatek,generic-tphy-v3
93      - const: mediatek,mt2701-u3phy
94        deprecated: true
95      - const: mediatek,mt2712-u3phy
96        deprecated: true
97      - const: mediatek,mt8173-u3phy
98
99  reg:
100    description:
101      Register shared by multiple ports, exclude port's private register.
102      It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
103      T-PHY V2/V3, such as mt2712.
104    maxItems: 1
105
106  "#address-cells":
107    enum: [1, 2]
108
109  "#size-cells":
110    enum: [1, 2]
111
112  # Used with non-empty value if optional 'reg' is not provided.
113  # The format of the value is an arbitrary number of triplets of
114  # (child-bus-address, parent-bus-address, length).
115  ranges: true
116
117  mediatek,src-ref-clk-mhz:
118    description:
119      Frequency of reference clock for slew rate calibrate
120    default: 26
121
122  mediatek,src-coef:
123    description:
124      Coefficient for slew rate calibrate, depends on SoC process
125    $ref: /schemas/types.yaml#/definitions/uint32
126    default: 28
127
128# Required child node:
129patternProperties:
130  "^(usb|pcie|sata)-phy@[0-9a-f]+$":
131    type: object
132    description:
133      A sub-node is required for each port the controller provides.
134      Address range information including the usual 'reg' property
135      is used inside these nodes to describe the controller's topology.
136
137    properties:
138      reg:
139        maxItems: 1
140
141      clocks:
142        minItems: 1
143        items:
144          - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
145          - description: Reference clock of analog phy
146        description:
147          Uses both clocks if the clock of analog and digital phys are
148          separated, otherwise uses "ref" clock only if needed.
149
150      clock-names:
151        minItems: 1
152        items:
153          - const: ref
154          - const: da_ref
155
156      "#phy-cells":
157        const: 1
158        description: |
159          The cells contain the following arguments.
160
161          - description: The PHY type
162              enum:
163                - PHY_TYPE_USB2
164                - PHY_TYPE_USB3
165                - PHY_TYPE_PCIE
166                - PHY_TYPE_SATA
167                - PHY_TYPE_SGMII
168
169      nvmem-cells:
170        items:
171          - description: internal R efuse for U2 PHY or U3/PCIe PHY
172          - description: rx_imp_sel efuse for U3/PCIe PHY
173          - description: tx_imp_sel efuse for U3/PCIe PHY
174        description: |
175          Phandles to nvmem cell that contains the efuse data;
176          Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
177          three items should be provided at the same time for U3/PCIe PHY,
178          when use software to load efuse;
179          If unspecified, will use hardware auto-load efuse.
180
181      nvmem-cell-names:
182        items:
183          - const: intr
184          - const: rx_imp
185          - const: tx_imp
186
187      # The following optional vendor properties are only for debug or HQA test
188      mediatek,eye-src:
189        description:
190          The value of slew rate calibrate (U2 phy)
191        $ref: /schemas/types.yaml#/definitions/uint32
192        minimum: 1
193        maximum: 7
194
195      mediatek,eye-vrt:
196        description:
197          The selection of VRT reference voltage (U2 phy)
198        $ref: /schemas/types.yaml#/definitions/uint32
199        minimum: 1
200        maximum: 7
201
202      mediatek,eye-term:
203        description:
204          The selection of HS_TX TERM reference voltage (U2 phy)
205        $ref: /schemas/types.yaml#/definitions/uint32
206        minimum: 1
207        maximum: 7
208
209      mediatek,intr:
210        description:
211          The selection of internal resistor (U2 phy)
212        $ref: /schemas/types.yaml#/definitions/uint32
213        minimum: 1
214        maximum: 31
215
216      mediatek,discth:
217        description:
218          The selection of disconnect threshold (U2 phy)
219        $ref: /schemas/types.yaml#/definitions/uint32
220        minimum: 1
221        maximum: 15
222
223      mediatek,pre-emphasis:
224        description:
225          The level of pre-emphasis which used to widen the eye opening and
226          boost eye swing, the unit step is about 4.16% increment; e.g. the
227          level 1 means amplitude increases about 4.16%, the level 2 is about
228          8.3% etc. (U2 phy)
229        $ref: /schemas/types.yaml#/definitions/uint32
230        minimum: 1
231        maximum: 3
232
233      mediatek,bc12:
234        description:
235          Specify the flag to enable BC1.2 if support it
236        type: boolean
237
238      mediatek,syscon-type:
239        $ref: /schemas/types.yaml#/definitions/phandle-array
240        maxItems: 1
241        description:
242          A phandle to syscon used to access the register of type switch,
243          the field should always be 3 cells long.
244        items:
245          items:
246            - description:
247                The first cell represents a phandle to syscon
248            - description:
249                The second cell represents the register offset
250            - description:
251                The third cell represents the index of config segment
252              enum: [0, 1, 2, 3]
253
254    required:
255      - reg
256      - "#phy-cells"
257
258    additionalProperties: false
259
260required:
261  - compatible
262  - "#address-cells"
263  - "#size-cells"
264  - ranges
265
266additionalProperties: false
267
268examples:
269  - |
270    #include <dt-bindings/clock/mt8173-clk.h>
271    #include <dt-bindings/interrupt-controller/arm-gic.h>
272    #include <dt-bindings/interrupt-controller/irq.h>
273    #include <dt-bindings/phy/phy.h>
274    usb@11271000 {
275        compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
276        reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
277        reg-names = "mac", "ippc";
278        phys = <&u2port0 PHY_TYPE_USB2>,
279               <&u3port0 PHY_TYPE_USB3>,
280               <&u2port1 PHY_TYPE_USB2>;
281        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
282        clocks = <&topckgen CLK_TOP_USB30_SEL>;
283        clock-names = "sys_ck";
284    };
285
286    t-phy@11290000 {
287        compatible = "mediatek,mt8173-u3phy";
288        reg = <0x11290000 0x800>;
289        #address-cells = <1>;
290        #size-cells = <1>;
291        ranges;
292
293        u2port0: usb-phy@11290800 {
294            reg = <0x11290800 0x100>;
295            clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
296            clock-names = "ref", "da_ref";
297            #phy-cells = <1>;
298        };
299
300        u3port0: usb-phy@11290900 {
301            reg = <0x11290900 0x700>;
302            clocks = <&clk26m>;
303            clock-names = "ref";
304            #phy-cells = <1>;
305        };
306
307        u2port1: usb-phy@11291000 {
308            reg = <0x11291000 0x100>;
309            #phy-cells = <1>;
310        };
311    };
312
313...
314