1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
9
10maintainers:
11  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12  - Philipp Zabel <p.zabel@pengutronix.de>
13  - Chunfeng Yun <chunfeng.yun@mediatek.com>
14
15description: |
16  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17  output and drives the HDMI pads.
18
19properties:
20  $nodename:
21    pattern: "^hdmi-phy@[0-9a-f]+$"
22
23  compatible:
24    enum:
25      - mediatek,mt2701-hdmi-phy
26      - mediatek,mt7623-hdmi-phy
27      - mediatek,mt8173-hdmi-phy
28
29  reg:
30    maxItems: 1
31
32  clocks:
33    items:
34      - description: PLL reference clock
35
36  clock-names:
37    items:
38      - const: pll_ref
39
40  clock-output-names:
41    items:
42      - const: hdmitx_dig_cts
43
44  "#phy-cells":
45    const: 0
46
47  "#clock-cells":
48    const: 0
49
50  mediatek,ibias:
51    description:
52      TX DRV bias current for < 1.65Gbps
53    $ref: /schemas/types.yaml#/definitions/uint32
54    minimum: 0
55    maximum: 63
56    default: 0xa
57
58  mediatek,ibias_up:
59    description:
60      TX DRV bias current for >= 1.65Gbps
61    $ref: /schemas/types.yaml#/definitions/uint32
62    minimum: 0
63    maximum: 63
64    default: 0x1c
65
66required:
67  - compatible
68  - reg
69  - clocks
70  - clock-names
71  - clock-output-names
72  - "#phy-cells"
73  - "#clock-cells"
74
75additionalProperties: false
76
77examples:
78  - |
79    #include <dt-bindings/clock/mt8173-clk.h>
80    hdmi_phy: hdmi-phy@10209100 {
81        compatible = "mediatek,mt8173-hdmi-phy";
82        reg = <0x10209100 0x24>;
83        clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
84        clock-names = "pll_ref";
85        clock-output-names = "hdmitx_dig_cts";
86        mediatek,ibias = <0xa>;
87        mediatek,ibias_up = <0x1c>;
88        #clock-cells = <0>;
89        #phy-cells = <0>;
90    };
91
92...
93