1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 MediaTek
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: MediaTek MIPI Display Serial Interface (DSI) PHY binding
9
10maintainers:
11  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12  - Philipp Zabel <p.zabel@pengutronix.de>
13  - Chunfeng Yun <chunfeng.yun@mediatek.com>
14
15description: The MIPI DSI PHY supports up to 4-lane output.
16
17properties:
18  $nodename:
19    pattern: "^dsi-phy@[0-9a-f]+$"
20
21  compatible:
22    enum:
23      - mediatek,mt2701-mipi-tx
24      - mediatek,mt7623-mipi-tx
25      - mediatek,mt8173-mipi-tx
26      - mediatek,mt8183-mipi-tx
27
28  reg:
29    maxItems: 1
30
31  clocks:
32    items:
33      - description: PLL reference clock
34
35  clock-output-names:
36    maxItems: 1
37
38  "#phy-cells":
39    const: 0
40
41  "#clock-cells":
42    const: 0
43
44  nvmem-cells:
45    maxItems: 1
46    description: A phandle to the calibration data provided by a nvmem device,
47      if unspecified, default values shall be used.
48
49  nvmem-cell-names:
50    items:
51      - const: calibration-data
52
53  drive-strength-microamp:
54    description: adjust driving current
55    multipleOf: 200
56    minimum: 2000
57    maximum: 6000
58    default: 4600
59
60required:
61  - compatible
62  - reg
63  - clocks
64  - clock-output-names
65  - "#phy-cells"
66  - "#clock-cells"
67
68additionalProperties: false
69
70examples:
71  - |
72    #include <dt-bindings/clock/mt8173-clk.h>
73    dsi-phy@10215000 {
74        compatible = "mediatek,mt8173-mipi-tx";
75        reg = <0x10215000 0x1000>;
76        clocks = <&clk26m>;
77        clock-output-names = "mipi_tx0_pll";
78        drive-strength-microamp = <4000>;
79        nvmem-cells= <&mipi_tx_calibration>;
80        nvmem-cell-names = "calibration-data";
81        #clock-cells = <0>;
82        #phy-cells = <0>;
83    };
84
85...
86