15ada755dSChunfeng Yun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 25ada755dSChunfeng Yun# Copyright (c) 2020 MediaTek 35ada755dSChunfeng Yun%YAML 1.2 45ada755dSChunfeng Yun--- 55ada755dSChunfeng Yun$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml# 65ada755dSChunfeng Yun$schema: http://devicetree.org/meta-schemas/core.yaml# 75ada755dSChunfeng Yun 85ada755dSChunfeng Yuntitle: MediaTek High Definition Multimedia Interface (HDMI) PHY binding 95ada755dSChunfeng Yun 105ada755dSChunfeng Yunmaintainers: 115ada755dSChunfeng Yun - Chun-Kuang Hu <chunkuang.hu@kernel.org> 125ada755dSChunfeng Yun - Philipp Zabel <p.zabel@pengutronix.de> 135ada755dSChunfeng Yun - Chunfeng Yun <chunfeng.yun@mediatek.com> 145ada755dSChunfeng Yun 155ada755dSChunfeng Yundescription: | 165ada755dSChunfeng Yun The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel 175ada755dSChunfeng Yun output and drives the HDMI pads. 185ada755dSChunfeng Yun 195ada755dSChunfeng Yunproperties: 205ada755dSChunfeng Yun $nodename: 215ada755dSChunfeng Yun pattern: "^hdmi-phy@[0-9a-f]+$" 225ada755dSChunfeng Yun 235ada755dSChunfeng Yun compatible: 24*9dbccfefSChunfeng Yun oneOf: 25*9dbccfefSChunfeng Yun - items: 26*9dbccfefSChunfeng Yun - enum: 275ada755dSChunfeng Yun - mediatek,mt7623-hdmi-phy 28*9dbccfefSChunfeng Yun - const: mediatek,mt2701-hdmi-phy 29*9dbccfefSChunfeng Yun - const: mediatek,mt2701-hdmi-phy 30*9dbccfefSChunfeng Yun - const: mediatek,mt8173-hdmi-phy 315ada755dSChunfeng Yun 325ada755dSChunfeng Yun reg: 335ada755dSChunfeng Yun maxItems: 1 345ada755dSChunfeng Yun 355ada755dSChunfeng Yun clocks: 365ada755dSChunfeng Yun items: 375ada755dSChunfeng Yun - description: PLL reference clock 385ada755dSChunfeng Yun 395ada755dSChunfeng Yun clock-names: 405ada755dSChunfeng Yun items: 415ada755dSChunfeng Yun - const: pll_ref 425ada755dSChunfeng Yun 435ada755dSChunfeng Yun clock-output-names: 445ada755dSChunfeng Yun items: 455ada755dSChunfeng Yun - const: hdmitx_dig_cts 465ada755dSChunfeng Yun 475ada755dSChunfeng Yun "#phy-cells": 485ada755dSChunfeng Yun const: 0 495ada755dSChunfeng Yun 505ada755dSChunfeng Yun "#clock-cells": 515ada755dSChunfeng Yun const: 0 525ada755dSChunfeng Yun 535ada755dSChunfeng Yun mediatek,ibias: 545ada755dSChunfeng Yun description: 555ada755dSChunfeng Yun TX DRV bias current for < 1.65Gbps 565ada755dSChunfeng Yun $ref: /schemas/types.yaml#/definitions/uint32 575ada755dSChunfeng Yun minimum: 0 585ada755dSChunfeng Yun maximum: 63 595ada755dSChunfeng Yun default: 0xa 605ada755dSChunfeng Yun 615ada755dSChunfeng Yun mediatek,ibias_up: 625ada755dSChunfeng Yun description: 635ada755dSChunfeng Yun TX DRV bias current for >= 1.65Gbps 645ada755dSChunfeng Yun $ref: /schemas/types.yaml#/definitions/uint32 655ada755dSChunfeng Yun minimum: 0 665ada755dSChunfeng Yun maximum: 63 675ada755dSChunfeng Yun default: 0x1c 685ada755dSChunfeng Yun 695ada755dSChunfeng Yunrequired: 705ada755dSChunfeng Yun - compatible 715ada755dSChunfeng Yun - reg 725ada755dSChunfeng Yun - clocks 735ada755dSChunfeng Yun - clock-names 745ada755dSChunfeng Yun - clock-output-names 755ada755dSChunfeng Yun - "#phy-cells" 765ada755dSChunfeng Yun - "#clock-cells" 775ada755dSChunfeng Yun 785ada755dSChunfeng YunadditionalProperties: false 795ada755dSChunfeng Yun 805ada755dSChunfeng Yunexamples: 815ada755dSChunfeng Yun - | 825ada755dSChunfeng Yun #include <dt-bindings/clock/mt8173-clk.h> 835ada755dSChunfeng Yun hdmi_phy: hdmi-phy@10209100 { 845ada755dSChunfeng Yun compatible = "mediatek,mt8173-hdmi-phy"; 855ada755dSChunfeng Yun reg = <0x10209100 0x24>; 865ada755dSChunfeng Yun clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 875ada755dSChunfeng Yun clock-names = "pll_ref"; 885ada755dSChunfeng Yun clock-output-names = "hdmitx_dig_cts"; 895ada755dSChunfeng Yun mediatek,ibias = <0xa>; 905ada755dSChunfeng Yun mediatek,ibias_up = <0x1c>; 915ada755dSChunfeng Yun #clock-cells = <0>; 925ada755dSChunfeng Yun #phy-cells = <0>; 935ada755dSChunfeng Yun }; 945ada755dSChunfeng Yun 955ada755dSChunfeng Yun... 96