1*5ada755dSChunfeng Yun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*5ada755dSChunfeng Yun# Copyright (c) 2020 MediaTek
3*5ada755dSChunfeng Yun%YAML 1.2
4*5ada755dSChunfeng Yun---
5*5ada755dSChunfeng Yun$id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6*5ada755dSChunfeng Yun$schema: http://devicetree.org/meta-schemas/core.yaml#
7*5ada755dSChunfeng Yun
8*5ada755dSChunfeng Yuntitle: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
9*5ada755dSChunfeng Yun
10*5ada755dSChunfeng Yunmaintainers:
11*5ada755dSChunfeng Yun  - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12*5ada755dSChunfeng Yun  - Philipp Zabel <p.zabel@pengutronix.de>
13*5ada755dSChunfeng Yun  - Chunfeng Yun <chunfeng.yun@mediatek.com>
14*5ada755dSChunfeng Yun
15*5ada755dSChunfeng Yundescription: |
16*5ada755dSChunfeng Yun  The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17*5ada755dSChunfeng Yun  output and drives the HDMI pads.
18*5ada755dSChunfeng Yun
19*5ada755dSChunfeng Yunproperties:
20*5ada755dSChunfeng Yun  $nodename:
21*5ada755dSChunfeng Yun    pattern: "^hdmi-phy@[0-9a-f]+$"
22*5ada755dSChunfeng Yun
23*5ada755dSChunfeng Yun  compatible:
24*5ada755dSChunfeng Yun    enum:
25*5ada755dSChunfeng Yun      - mediatek,mt2701-hdmi-phy
26*5ada755dSChunfeng Yun      - mediatek,mt7623-hdmi-phy
27*5ada755dSChunfeng Yun      - mediatek,mt8173-hdmi-phy
28*5ada755dSChunfeng Yun
29*5ada755dSChunfeng Yun  reg:
30*5ada755dSChunfeng Yun    maxItems: 1
31*5ada755dSChunfeng Yun
32*5ada755dSChunfeng Yun  clocks:
33*5ada755dSChunfeng Yun    items:
34*5ada755dSChunfeng Yun      - description: PLL reference clock
35*5ada755dSChunfeng Yun
36*5ada755dSChunfeng Yun  clock-names:
37*5ada755dSChunfeng Yun    items:
38*5ada755dSChunfeng Yun      - const: pll_ref
39*5ada755dSChunfeng Yun
40*5ada755dSChunfeng Yun  clock-output-names:
41*5ada755dSChunfeng Yun    items:
42*5ada755dSChunfeng Yun      - const: hdmitx_dig_cts
43*5ada755dSChunfeng Yun
44*5ada755dSChunfeng Yun  "#phy-cells":
45*5ada755dSChunfeng Yun    const: 0
46*5ada755dSChunfeng Yun
47*5ada755dSChunfeng Yun  "#clock-cells":
48*5ada755dSChunfeng Yun    const: 0
49*5ada755dSChunfeng Yun
50*5ada755dSChunfeng Yun  mediatek,ibias:
51*5ada755dSChunfeng Yun    description:
52*5ada755dSChunfeng Yun      TX DRV bias current for < 1.65Gbps
53*5ada755dSChunfeng Yun    $ref: /schemas/types.yaml#/definitions/uint32
54*5ada755dSChunfeng Yun    minimum: 0
55*5ada755dSChunfeng Yun    maximum: 63
56*5ada755dSChunfeng Yun    default: 0xa
57*5ada755dSChunfeng Yun
58*5ada755dSChunfeng Yun  mediatek,ibias_up:
59*5ada755dSChunfeng Yun    description:
60*5ada755dSChunfeng Yun      TX DRV bias current for >= 1.65Gbps
61*5ada755dSChunfeng Yun    $ref: /schemas/types.yaml#/definitions/uint32
62*5ada755dSChunfeng Yun    minimum: 0
63*5ada755dSChunfeng Yun    maximum: 63
64*5ada755dSChunfeng Yun    default: 0x1c
65*5ada755dSChunfeng Yun
66*5ada755dSChunfeng Yunrequired:
67*5ada755dSChunfeng Yun  - compatible
68*5ada755dSChunfeng Yun  - reg
69*5ada755dSChunfeng Yun  - clocks
70*5ada755dSChunfeng Yun  - clock-names
71*5ada755dSChunfeng Yun  - clock-output-names
72*5ada755dSChunfeng Yun  - "#phy-cells"
73*5ada755dSChunfeng Yun  - "#clock-cells"
74*5ada755dSChunfeng Yun
75*5ada755dSChunfeng YunadditionalProperties: false
76*5ada755dSChunfeng Yun
77*5ada755dSChunfeng Yunexamples:
78*5ada755dSChunfeng Yun  - |
79*5ada755dSChunfeng Yun    #include <dt-bindings/clock/mt8173-clk.h>
80*5ada755dSChunfeng Yun    hdmi_phy: hdmi-phy@10209100 {
81*5ada755dSChunfeng Yun        compatible = "mediatek,mt8173-hdmi-phy";
82*5ada755dSChunfeng Yun        reg = <0x10209100 0x24>;
83*5ada755dSChunfeng Yun        clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
84*5ada755dSChunfeng Yun        clock-names = "pll_ref";
85*5ada755dSChunfeng Yun        clock-output-names = "hdmitx_dig_cts";
86*5ada755dSChunfeng Yun        mediatek,ibias = <0xa>;
87*5ada755dSChunfeng Yun        mediatek,ibias_up = <0x1c>;
88*5ada755dSChunfeng Yun        #clock-cells = <0>;
89*5ada755dSChunfeng Yun        #phy-cells = <0>;
90*5ada755dSChunfeng Yun    };
91*5ada755dSChunfeng Yun
92*5ada755dSChunfeng Yun...
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