1*dc8423a8SChunfeng Yun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*dc8423a8SChunfeng Yun# Copyright (c) 2020 MediaTek 3*dc8423a8SChunfeng Yun%YAML 1.2 4*dc8423a8SChunfeng Yun--- 5*dc8423a8SChunfeng Yun$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml# 6*dc8423a8SChunfeng Yun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*dc8423a8SChunfeng Yun 8*dc8423a8SChunfeng Yuntitle: MediaTek MIPI Display Serial Interface (DSI) PHY binding 9*dc8423a8SChunfeng Yun 10*dc8423a8SChunfeng Yunmaintainers: 11*dc8423a8SChunfeng Yun - Chun-Kuang Hu <chunkuang.hu@kernel.org> 12*dc8423a8SChunfeng Yun - Philipp Zabel <p.zabel@pengutronix.de> 13*dc8423a8SChunfeng Yun - Chunfeng Yun <chunfeng.yun@mediatek.com> 14*dc8423a8SChunfeng Yun 15*dc8423a8SChunfeng Yundescription: The MIPI DSI PHY supports up to 4-lane output. 16*dc8423a8SChunfeng Yun 17*dc8423a8SChunfeng Yunproperties: 18*dc8423a8SChunfeng Yun $nodename: 19*dc8423a8SChunfeng Yun pattern: "^dsi-phy@[0-9a-f]+$" 20*dc8423a8SChunfeng Yun 21*dc8423a8SChunfeng Yun compatible: 22*dc8423a8SChunfeng Yun enum: 23*dc8423a8SChunfeng Yun - mediatek,mt2701-mipi-tx 24*dc8423a8SChunfeng Yun - mediatek,mt7623-mipi-tx 25*dc8423a8SChunfeng Yun - mediatek,mt8173-mipi-tx 26*dc8423a8SChunfeng Yun - mediatek,mt8183-mipi-tx 27*dc8423a8SChunfeng Yun 28*dc8423a8SChunfeng Yun reg: 29*dc8423a8SChunfeng Yun maxItems: 1 30*dc8423a8SChunfeng Yun 31*dc8423a8SChunfeng Yun clocks: 32*dc8423a8SChunfeng Yun items: 33*dc8423a8SChunfeng Yun - description: PLL reference clock 34*dc8423a8SChunfeng Yun 35*dc8423a8SChunfeng Yun clock-output-names: 36*dc8423a8SChunfeng Yun maxItems: 1 37*dc8423a8SChunfeng Yun 38*dc8423a8SChunfeng Yun "#phy-cells": 39*dc8423a8SChunfeng Yun const: 0 40*dc8423a8SChunfeng Yun 41*dc8423a8SChunfeng Yun "#clock-cells": 42*dc8423a8SChunfeng Yun const: 0 43*dc8423a8SChunfeng Yun 44*dc8423a8SChunfeng Yun nvmem-cells: 45*dc8423a8SChunfeng Yun maxItems: 1 46*dc8423a8SChunfeng Yun description: A phandle to the calibration data provided by a nvmem device, 47*dc8423a8SChunfeng Yun if unspecified, default values shall be used. 48*dc8423a8SChunfeng Yun 49*dc8423a8SChunfeng Yun nvmem-cell-names: 50*dc8423a8SChunfeng Yun items: 51*dc8423a8SChunfeng Yun - const: calibration-data 52*dc8423a8SChunfeng Yun 53*dc8423a8SChunfeng Yun drive-strength-microamp: 54*dc8423a8SChunfeng Yun description: adjust driving current 55*dc8423a8SChunfeng Yun multipleOf: 200 56*dc8423a8SChunfeng Yun minimum: 2000 57*dc8423a8SChunfeng Yun maximum: 6000 58*dc8423a8SChunfeng Yun default: 4600 59*dc8423a8SChunfeng Yun 60*dc8423a8SChunfeng Yunrequired: 61*dc8423a8SChunfeng Yun - compatible 62*dc8423a8SChunfeng Yun - reg 63*dc8423a8SChunfeng Yun - clocks 64*dc8423a8SChunfeng Yun - clock-output-names 65*dc8423a8SChunfeng Yun - "#phy-cells" 66*dc8423a8SChunfeng Yun - "#clock-cells" 67*dc8423a8SChunfeng Yun 68*dc8423a8SChunfeng YunadditionalProperties: false 69*dc8423a8SChunfeng Yun 70*dc8423a8SChunfeng Yunexamples: 71*dc8423a8SChunfeng Yun - | 72*dc8423a8SChunfeng Yun #include <dt-bindings/clock/mt8173-clk.h> 73*dc8423a8SChunfeng Yun dsi-phy@10215000 { 74*dc8423a8SChunfeng Yun compatible = "mediatek,mt8173-mipi-tx"; 75*dc8423a8SChunfeng Yun reg = <0x10215000 0x1000>; 76*dc8423a8SChunfeng Yun clocks = <&clk26m>; 77*dc8423a8SChunfeng Yun clock-output-names = "mipi_tx0_pll"; 78*dc8423a8SChunfeng Yun drive-strength-microamp = <4000>; 79*dc8423a8SChunfeng Yun nvmem-cells= <&mipi_tx_calibration>; 80*dc8423a8SChunfeng Yun nvmem-cell-names = "calibration-data"; 81*dc8423a8SChunfeng Yun #clock-cells = <0>; 82*dc8423a8SChunfeng Yun #phy-cells = <0>; 83*dc8423a8SChunfeng Yun }; 84*dc8423a8SChunfeng Yun 85*dc8423a8SChunfeng Yun... 86