1dc8423a8SChunfeng Yun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2dc8423a8SChunfeng Yun# Copyright (c) 2020 MediaTek 3dc8423a8SChunfeng Yun%YAML 1.2 4dc8423a8SChunfeng Yun--- 5dc8423a8SChunfeng Yun$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml# 6dc8423a8SChunfeng Yun$schema: http://devicetree.org/meta-schemas/core.yaml# 7dc8423a8SChunfeng Yun 8dc8423a8SChunfeng Yuntitle: MediaTek MIPI Display Serial Interface (DSI) PHY binding 9dc8423a8SChunfeng Yun 10dc8423a8SChunfeng Yunmaintainers: 11dc8423a8SChunfeng Yun - Chun-Kuang Hu <chunkuang.hu@kernel.org> 12dc8423a8SChunfeng Yun - Philipp Zabel <p.zabel@pengutronix.de> 13dc8423a8SChunfeng Yun - Chunfeng Yun <chunfeng.yun@mediatek.com> 14dc8423a8SChunfeng Yun 15dc8423a8SChunfeng Yundescription: The MIPI DSI PHY supports up to 4-lane output. 16dc8423a8SChunfeng Yun 17dc8423a8SChunfeng Yunproperties: 18dc8423a8SChunfeng Yun $nodename: 19dc8423a8SChunfeng Yun pattern: "^dsi-phy@[0-9a-f]+$" 20dc8423a8SChunfeng Yun 21dc8423a8SChunfeng Yun compatible: 22*66b87358SChunfeng Yun oneOf: 23*66b87358SChunfeng Yun - items: 24*66b87358SChunfeng Yun - enum: 25dc8423a8SChunfeng Yun - mediatek,mt7623-mipi-tx 26*66b87358SChunfeng Yun - const: mediatek,mt2701-mipi-tx 27*66b87358SChunfeng Yun - const: mediatek,mt2701-mipi-tx 28*66b87358SChunfeng Yun - const: mediatek,mt8173-mipi-tx 29*66b87358SChunfeng Yun - const: mediatek,mt8183-mipi-tx 30dc8423a8SChunfeng Yun 31dc8423a8SChunfeng Yun reg: 32dc8423a8SChunfeng Yun maxItems: 1 33dc8423a8SChunfeng Yun 34dc8423a8SChunfeng Yun clocks: 35dc8423a8SChunfeng Yun items: 36dc8423a8SChunfeng Yun - description: PLL reference clock 37dc8423a8SChunfeng Yun 38dc8423a8SChunfeng Yun clock-output-names: 39dc8423a8SChunfeng Yun maxItems: 1 40dc8423a8SChunfeng Yun 41dc8423a8SChunfeng Yun "#phy-cells": 42dc8423a8SChunfeng Yun const: 0 43dc8423a8SChunfeng Yun 44dc8423a8SChunfeng Yun "#clock-cells": 45dc8423a8SChunfeng Yun const: 0 46dc8423a8SChunfeng Yun 47dc8423a8SChunfeng Yun nvmem-cells: 48dc8423a8SChunfeng Yun maxItems: 1 49dc8423a8SChunfeng Yun description: A phandle to the calibration data provided by a nvmem device, 50dc8423a8SChunfeng Yun if unspecified, default values shall be used. 51dc8423a8SChunfeng Yun 52dc8423a8SChunfeng Yun nvmem-cell-names: 53dc8423a8SChunfeng Yun items: 54dc8423a8SChunfeng Yun - const: calibration-data 55dc8423a8SChunfeng Yun 56dc8423a8SChunfeng Yun drive-strength-microamp: 57dc8423a8SChunfeng Yun description: adjust driving current 58dc8423a8SChunfeng Yun multipleOf: 200 59dc8423a8SChunfeng Yun minimum: 2000 60dc8423a8SChunfeng Yun maximum: 6000 61dc8423a8SChunfeng Yun default: 4600 62dc8423a8SChunfeng Yun 63dc8423a8SChunfeng Yunrequired: 64dc8423a8SChunfeng Yun - compatible 65dc8423a8SChunfeng Yun - reg 66dc8423a8SChunfeng Yun - clocks 67dc8423a8SChunfeng Yun - clock-output-names 68dc8423a8SChunfeng Yun - "#phy-cells" 69dc8423a8SChunfeng Yun - "#clock-cells" 70dc8423a8SChunfeng Yun 71dc8423a8SChunfeng YunadditionalProperties: false 72dc8423a8SChunfeng Yun 73dc8423a8SChunfeng Yunexamples: 74dc8423a8SChunfeng Yun - | 75dc8423a8SChunfeng Yun #include <dt-bindings/clock/mt8173-clk.h> 76dc8423a8SChunfeng Yun dsi-phy@10215000 { 77dc8423a8SChunfeng Yun compatible = "mediatek,mt8173-mipi-tx"; 78dc8423a8SChunfeng Yun reg = <0x10215000 0x1000>; 79dc8423a8SChunfeng Yun clocks = <&clk26m>; 80dc8423a8SChunfeng Yun clock-output-names = "mipi_tx0_pll"; 81dc8423a8SChunfeng Yun drive-strength-microamp = <4000>; 82dc8423a8SChunfeng Yun nvmem-cells= <&mipi_tx_calibration>; 83dc8423a8SChunfeng Yun nvmem-cell-names = "calibration-data"; 84dc8423a8SChunfeng Yun #clock-cells = <0>; 85dc8423a8SChunfeng Yun #phy-cells = <0>; 86dc8423a8SChunfeng Yun }; 87dc8423a8SChunfeng Yun 88dc8423a8SChunfeng Yun... 89