1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: HiSilicon Kirin970 PCIe PHY 8 9maintainers: 10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org> 11 12description: |+ 13 Bindings for PCIe PHY on HiSilicon Kirin 970. 14 15properties: 16 compatible: 17 const: hisilicon,hi970-pcie-phy 18 19 "#phy-cells": 20 const: 0 21 22 reg: 23 maxItems: 1 24 description: PHY Control registers 25 26 phy-supply: 27 description: The PCIe PHY power supply 28 29 clocks: 30 items: 31 - description: PCIe PHY clock 32 - description: PCIe AUX clock 33 - description: PCIe APB PHY clock 34 - description: PCIe APB SYS clock 35 - description: PCIe ACLK clock 36 37 clock-names: 38 items: 39 - const: phy_ref 40 - const: aux 41 - const: apb_phy 42 - const: apb_sys 43 - const: aclk 44 45 hisilicon,eye-diagram-param: 46 $ref: /schemas/types.yaml#/definitions/uint32-array 47 description: Eye diagram for phy. 48 49required: 50 - "#phy-cells" 51 - compatible 52 - reg 53 - clocks 54 - clock-names 55 - hisilicon,eye-diagram-param 56 - phy-supply 57 58additionalProperties: false 59 60examples: 61 - | 62 #include <dt-bindings/clock/hi3670-clock.h> 63 64 soc { 65 #address-cells = <2>; 66 #size-cells = <2>; 67 pcie_phy: pcie-phy@fc000000 { 68 compatible = "hisilicon,hi970-pcie-phy"; 69 reg = <0x0 0xfc000000 0x0 0x80000>; 70 #phy-cells = <0>; 71 phy-supply = <&ldo33>; 72 clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>, 73 <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>, 74 <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>, 75 <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>, 76 <&crg_ctrl HI3670_ACLK_GATE_PCIE>; 77 clock-names = "phy_ref", "aux", 78 "apb_phy", "apb_sys", "aclk"; 79 hisilicon,eye-diagram-param = <0xffffffff 0xffffffff 80 0xffffffff 0xffffffff 0xffffffff>; 81 }; 82 }; 83