1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Allwinner A31 MIPI D-PHY Controller 8 9maintainers: 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 12 13properties: 14 "#phy-cells": 15 const: 0 16 17 compatible: 18 oneOf: 19 - const: allwinner,sun6i-a31-mipi-dphy 20 - items: 21 - const: allwinner,sun50i-a64-mipi-dphy 22 - const: allwinner,sun6i-a31-mipi-dphy 23 24 reg: 25 maxItems: 1 26 27 interrupts: 28 maxItems: 1 29 30 clocks: 31 items: 32 - description: Bus Clock 33 - description: Module Clock 34 35 clock-names: 36 items: 37 - const: bus 38 - const: mod 39 40 resets: 41 maxItems: 1 42 43 allwinner,direction: 44 $ref: '/schemas/types.yaml#/definitions/string' 45 description: | 46 Direction of the D-PHY: 47 - "rx" for receiving (e.g. when used with MIPI CSI-2); 48 - "tx" for transmitting (e.g. when used with MIPI DSI). 49 50 enum: 51 - tx 52 - rx 53 default: tx 54 55required: 56 - "#phy-cells" 57 - compatible 58 - reg 59 - interrupts 60 - clocks 61 - clock-names 62 - resets 63 64additionalProperties: false 65 66examples: 67 - | 68 #include <dt-bindings/interrupt-controller/arm-gic.h> 69 70 dphy0: d-phy@1ca1000 { 71 compatible = "allwinner,sun6i-a31-mipi-dphy"; 72 reg = <0x01ca1000 0x1000>; 73 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 74 clocks = <&ccu 23>, <&ccu 97>; 75 clock-names = "bus", "mod"; 76 resets = <&ccu 4>; 77 #phy-cells = <0>; 78 }; 79 80... 81