1*7e38085dSConor Dooley# SPDX-License-Identifier: BSD-2-Clause 2*7e38085dSConor Dooley%YAML 1.2 3*7e38085dSConor Dooley--- 4*7e38085dSConor Dooley$id: http://devicetree.org/schemas/perf/riscv,pmu.yaml# 5*7e38085dSConor Dooley$schema: http://devicetree.org/meta-schemas/core.yaml# 6*7e38085dSConor Dooley 7*7e38085dSConor Dooleytitle: RISC-V SBI PMU events 8*7e38085dSConor Dooley 9*7e38085dSConor Dooleymaintainers: 10*7e38085dSConor Dooley - Atish Patra <atishp@rivosinc.com> 11*7e38085dSConor Dooley 12*7e38085dSConor Dooleydescription: | 13*7e38085dSConor Dooley The SBI PMU extension allows supervisor software to configure, start and 14*7e38085dSConor Dooley stop any performance counter at anytime. Thus, a user can leverage all 15*7e38085dSConor Dooley capabilities of performance analysis tools, such as perf, if the SBI PMU 16*7e38085dSConor Dooley extension is enabled. The following constraints apply: 17*7e38085dSConor Dooley 18*7e38085dSConor Dooley The platform must provide information about PMU event to counter mappings 19*7e38085dSConor Dooley either via device tree or another way, specific to the platform. 20*7e38085dSConor Dooley Without the event to counter mappings, the SBI PMU extension cannot be used. 21*7e38085dSConor Dooley 22*7e38085dSConor Dooley Platforms should provide information about the PMU event selector values 23*7e38085dSConor Dooley that should be encoded in the expected value of MHPMEVENTx while configuring 24*7e38085dSConor Dooley MHPMCOUNTERx for that specific event. The can either be done via device tree 25*7e38085dSConor Dooley or another way, specific to the platform. 26*7e38085dSConor Dooley The exact value to be written to MHPMEVENTx is completely dependent on the 27*7e38085dSConor Dooley platform. 28*7e38085dSConor Dooley 29*7e38085dSConor Dooley For information on the SBI specification see the section "Performance 30*7e38085dSConor Dooley Monitoring Unit Extension" of: 31*7e38085dSConor Dooley https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc 32*7e38085dSConor Dooley 33*7e38085dSConor Dooleyproperties: 34*7e38085dSConor Dooley compatible: 35*7e38085dSConor Dooley const: riscv,pmu 36*7e38085dSConor Dooley 37*7e38085dSConor Dooley riscv,event-to-mhpmevent: 38*7e38085dSConor Dooley $ref: /schemas/types.yaml#/definitions/uint32-matrix 39*7e38085dSConor Dooley description: 40*7e38085dSConor Dooley Represents an ONE-to-ONE mapping between a PMU event and the event 41*7e38085dSConor Dooley selector value that the platform expects to be written to the MHPMEVENTx 42*7e38085dSConor Dooley CSR for that event. 43*7e38085dSConor Dooley The mapping is encoded in an matrix format where each element represents 44*7e38085dSConor Dooley an event. 45*7e38085dSConor Dooley This property shouldn't encode any raw hardware event. 46*7e38085dSConor Dooley items: 47*7e38085dSConor Dooley items: 48*7e38085dSConor Dooley - description: event_idx, a 20-bit wide encoding of the event type and 49*7e38085dSConor Dooley code. Refer to the SBI specification for a complete description of 50*7e38085dSConor Dooley the event types and codes. 51*7e38085dSConor Dooley - description: upper 32 bits of the event selector value for MHPMEVENTx 52*7e38085dSConor Dooley - description: lower 32 bits of the event selector value for MHPMEVENTx 53*7e38085dSConor Dooley 54*7e38085dSConor Dooley riscv,event-to-mhpmcounters: 55*7e38085dSConor Dooley $ref: /schemas/types.yaml#/definitions/uint32-matrix 56*7e38085dSConor Dooley description: 57*7e38085dSConor Dooley Represents a MANY-to-MANY mapping between a range of events and all the 58*7e38085dSConor Dooley MHPMCOUNTERx in a bitmap format that can be used to monitor these range 59*7e38085dSConor Dooley of events. The information is encoded in an matrix format where each 60*7e38085dSConor Dooley element represents a certain range of events and corresponding counters. 61*7e38085dSConor Dooley This property shouldn't encode any raw event. 62*7e38085dSConor Dooley items: 63*7e38085dSConor Dooley items: 64*7e38085dSConor Dooley - description: first event_idx of the range of events 65*7e38085dSConor Dooley - description: last event_idx of the range of events 66*7e38085dSConor Dooley - description: bitmap of MHPMCOUNTERx for this event 67*7e38085dSConor Dooley 68*7e38085dSConor Dooley riscv,raw-event-to-mhpmcounters: 69*7e38085dSConor Dooley $ref: /schemas/types.yaml#/definitions/uint32-matrix 70*7e38085dSConor Dooley description: 71*7e38085dSConor Dooley Represents an ONE-to-MANY or MANY-to-MANY mapping between the rawevent(s) 72*7e38085dSConor Dooley and all the MHPMCOUNTERx in a bitmap format that can be used to monitor 73*7e38085dSConor Dooley that raw event. 74*7e38085dSConor Dooley The encoding of the raw events are platform specific. The information is 75*7e38085dSConor Dooley encoded in a matrix format where each element represents the specific raw 76*7e38085dSConor Dooley event(s). 77*7e38085dSConor Dooley If a platform directly encodes each raw PMU event as a unique ID, the 78*7e38085dSConor Dooley value of variant must be 0xffffffff_ffffffff. 79*7e38085dSConor Dooley items: 80*7e38085dSConor Dooley items: 81*7e38085dSConor Dooley - description: 82*7e38085dSConor Dooley upper 32 invariant bits for the range of events 83*7e38085dSConor Dooley - description: 84*7e38085dSConor Dooley lower 32 invariant bits for the range of events 85*7e38085dSConor Dooley - description: 86*7e38085dSConor Dooley upper 32 bits of the variant bit mask for the range of events 87*7e38085dSConor Dooley - description: 88*7e38085dSConor Dooley lower 32 bits of the variant bit mask for the range of events 89*7e38085dSConor Dooley - description: 90*7e38085dSConor Dooley bitmap of all MHPMCOUNTERx that can monitor the range of events 91*7e38085dSConor Dooley 92*7e38085dSConor Dooleydependencies: 93*7e38085dSConor Dooley "riscv,event-to-mhpmevent": [ "riscv,event-to-mhpmcounters" ] 94*7e38085dSConor Dooley "riscv,event-to-mhpmcounters": [ "riscv,event-to-mhpmevent" ] 95*7e38085dSConor Dooley 96*7e38085dSConor Dooleyrequired: 97*7e38085dSConor Dooley - compatible 98*7e38085dSConor Dooley 99*7e38085dSConor DooleyadditionalProperties: false 100*7e38085dSConor Dooley 101*7e38085dSConor Dooleyexamples: 102*7e38085dSConor Dooley - | 103*7e38085dSConor Dooley pmu { 104*7e38085dSConor Dooley compatible = "riscv,pmu"; 105*7e38085dSConor Dooley riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>; 106*7e38085dSConor Dooley riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>, 107*7e38085dSConor Dooley <0x00002 0x00002 0x00000004>, 108*7e38085dSConor Dooley <0x00003 0x0000A 0x00000ff8>, 109*7e38085dSConor Dooley <0x10000 0x10033 0x000ff000>; 110*7e38085dSConor Dooley riscv,raw-event-to-mhpmcounters = 111*7e38085dSConor Dooley /* For event ID 0x0002 */ 112*7e38085dSConor Dooley <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>, 113*7e38085dSConor Dooley /* For event ID 0-4 */ 114*7e38085dSConor Dooley <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>, 115*7e38085dSConor Dooley /* For event ID 0xffffffff0000000f - 0xffffffff000000ff */ 116*7e38085dSConor Dooley <0xffffffff 0x0 0xffffffff 0xffffff0f 0x00000ff0>; 117*7e38085dSConor Dooley }; 118*7e38085dSConor Dooley 119*7e38085dSConor Dooley - | 120*7e38085dSConor Dooley /* 121*7e38085dSConor Dooley * For HiFive Unmatched board the encodings can be found here 122*7e38085dSConor Dooley * https://sifive.cdn.prismic.io/sifive/1a82e600-1f93-4f41-b2d8-86ed8b16acba_fu740-c000-manual-v1p6.pdf 123*7e38085dSConor Dooley * 124*7e38085dSConor Dooley * This example also binds standard SBI PMU hardware IDs to U74 PMU event 125*7e38085dSConor Dooley * codes, U74 uses a bitfield for events encoding, so several U74 events 126*7e38085dSConor Dooley * can be bound to a single perf ID. 127*7e38085dSConor Dooley * See SBI PMU hardware IDs in arch/riscv/include/asm/sbi.h 128*7e38085dSConor Dooley */ 129*7e38085dSConor Dooley pmu { 130*7e38085dSConor Dooley compatible = "riscv,pmu"; 131*7e38085dSConor Dooley riscv,event-to-mhpmevent = 132*7e38085dSConor Dooley /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */ 133*7e38085dSConor Dooley <0x00003 0x00000000 0x1801>, 134*7e38085dSConor Dooley /* SBI_PMU_HW_CACHE_MISSES -> Instruction or Data cache miss or MMIO access */ 135*7e38085dSConor Dooley <0x00004 0x00000000 0x0302>, 136*7e38085dSConor Dooley /* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */ 137*7e38085dSConor Dooley <0x00005 0x00000000 0x4000>, 138*7e38085dSConor Dooley /* SBI_PMU_HW_BRANCH_MISSES -> Branch or jump misprediction */ 139*7e38085dSConor Dooley <0x00006 0x00000000 0x6001>, 140*7e38085dSConor Dooley /* L1D_READ_MISS -> Data cache miss or MMIO access */ 141*7e38085dSConor Dooley <0x10001 0x00000000 0x0202>, 142*7e38085dSConor Dooley /* L1D_WRITE_ACCESS -> Data cache write-back */ 143*7e38085dSConor Dooley <0x10002 0x00000000 0x0402>, 144*7e38085dSConor Dooley /* L1I_READ_ACCESS -> Instruction cache miss */ 145*7e38085dSConor Dooley <0x10009 0x00000000 0x0102>, 146*7e38085dSConor Dooley /* LL_READ_MISS -> UTLB miss */ 147*7e38085dSConor Dooley <0x10011 0x00000000 0x2002>, 148*7e38085dSConor Dooley /* DTLB_READ_MISS -> Data TLB miss */ 149*7e38085dSConor Dooley <0x10019 0x00000000 0x1002>, 150*7e38085dSConor Dooley /* ITLB_READ_MISS-> Instruction TLB miss */ 151*7e38085dSConor Dooley <0x10021 0x00000000 0x0802>; 152*7e38085dSConor Dooley riscv,event-to-mhpmcounters = <0x00003 0x00006 0x18>, 153*7e38085dSConor Dooley <0x10001 0x10002 0x18>, 154*7e38085dSConor Dooley <0x10009 0x10009 0x18>, 155*7e38085dSConor Dooley <0x10011 0x10011 0x18>, 156*7e38085dSConor Dooley <0x10019 0x10019 0x18>, 157*7e38085dSConor Dooley <0x10021 0x10021 0x18>; 158*7e38085dSConor Dooley riscv,raw-event-to-mhpmcounters = <0x0 0x0 0xffffffff 0xfc0000ff 0x18>, 159*7e38085dSConor Dooley <0x0 0x1 0xffffffff 0xfff800ff 0x18>, 160*7e38085dSConor Dooley <0x0 0x2 0xffffffff 0xffffe0ff 0x18>; 161*7e38085dSConor Dooley }; 162