1*4cbf4772SBhaskara Budiredla# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4cbf4772SBhaskara Budiredla%YAML 1.2 3*4cbf4772SBhaskara Budiredla--- 4*4cbf4772SBhaskara Budiredla$id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml# 5*4cbf4772SBhaskara Budiredla$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4cbf4772SBhaskara Budiredla 7*4cbf4772SBhaskara Budiredlatitle: Marvell CN10K LLC-TAD performance monitor 8*4cbf4772SBhaskara Budiredla 9*4cbf4772SBhaskara Budiredlamaintainers: 10*4cbf4772SBhaskara Budiredla - Bhaskara Budiredla <bbudiredla@marvell.com> 11*4cbf4772SBhaskara Budiredla 12*4cbf4772SBhaskara Budiredladescription: | 13*4cbf4772SBhaskara Budiredla The Tag-and-Data units (TADs) maintain coherence and contain CN10K 14*4cbf4772SBhaskara Budiredla shared on-chip last level cache (LLC). The tad pmu measures the 15*4cbf4772SBhaskara Budiredla performance of last-level cache. Each tad pmu supports up to eight 16*4cbf4772SBhaskara Budiredla counters. 17*4cbf4772SBhaskara Budiredla 18*4cbf4772SBhaskara Budiredla The DT setup comprises of number of tad blocks, the sizes of pmu 19*4cbf4772SBhaskara Budiredla regions, tad blocks and overall base address of the HW. 20*4cbf4772SBhaskara Budiredla 21*4cbf4772SBhaskara Budiredlaproperties: 22*4cbf4772SBhaskara Budiredla compatible: 23*4cbf4772SBhaskara Budiredla const: marvell,cn10k-tad-pmu 24*4cbf4772SBhaskara Budiredla 25*4cbf4772SBhaskara Budiredla reg: 26*4cbf4772SBhaskara Budiredla maxItems: 1 27*4cbf4772SBhaskara Budiredla 28*4cbf4772SBhaskara Budiredla marvell,tad-cnt: 29*4cbf4772SBhaskara Budiredla description: specifies the number of tads on the soc 30*4cbf4772SBhaskara Budiredla $ref: /schemas/types.yaml#/definitions/uint32 31*4cbf4772SBhaskara Budiredla 32*4cbf4772SBhaskara Budiredla marvell,tad-page-size: 33*4cbf4772SBhaskara Budiredla description: specifies the size of each tad page 34*4cbf4772SBhaskara Budiredla $ref: /schemas/types.yaml#/definitions/uint32 35*4cbf4772SBhaskara Budiredla 36*4cbf4772SBhaskara Budiredla marvell,tad-pmu-page-size: 37*4cbf4772SBhaskara Budiredla description: specifies the size of page that the pmu uses 38*4cbf4772SBhaskara Budiredla $ref: /schemas/types.yaml#/definitions/uint32 39*4cbf4772SBhaskara Budiredla 40*4cbf4772SBhaskara Budiredlarequired: 41*4cbf4772SBhaskara Budiredla - compatible 42*4cbf4772SBhaskara Budiredla - reg 43*4cbf4772SBhaskara Budiredla - marvell,tad-cnt 44*4cbf4772SBhaskara Budiredla - marvell,tad-page-size 45*4cbf4772SBhaskara Budiredla - marvell,tad-pmu-page-size 46*4cbf4772SBhaskara Budiredla 47*4cbf4772SBhaskara BudiredlaadditionalProperties: false 48*4cbf4772SBhaskara Budiredla 49*4cbf4772SBhaskara Budiredlaexamples: 50*4cbf4772SBhaskara Budiredla - | 51*4cbf4772SBhaskara Budiredla 52*4cbf4772SBhaskara Budiredla tad { 53*4cbf4772SBhaskara Budiredla #address-cells = <2>; 54*4cbf4772SBhaskara Budiredla #size-cells = <2>; 55*4cbf4772SBhaskara Budiredla 56*4cbf4772SBhaskara Budiredla tad_pmu@80000000 { 57*4cbf4772SBhaskara Budiredla compatible = "marvell,cn10k-tad-pmu"; 58*4cbf4772SBhaskara Budiredla reg = <0x87e2 0x80000000 0x0 0x1000>; 59*4cbf4772SBhaskara Budiredla marvell,tad-cnt = <1>; 60*4cbf4772SBhaskara Budiredla marvell,tad-page-size = <0x1000>; 61*4cbf4772SBhaskara Budiredla marvell,tad-pmu-page-size = <0x1000>; 62*4cbf4772SBhaskara Budiredla }; 63*4cbf4772SBhaskara Budiredla }; 64