1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/versatile.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Versatile Platform Baseboard PCI interface
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11
12description: |+
13  PCI host controller found on the ARM Versatile PB board's FPGA.
14
15allOf:
16  - $ref: /schemas/pci/pci-bus.yaml#
17
18properties:
19  compatible:
20    const: arm,versatile-pci
21
22  reg:
23    items:
24      - description: Versatile-specific registers
25      - description: Self Config space
26      - description: Config space
27
28  ranges:
29    maxItems: 3
30
31  "#interrupt-cells": true
32
33  interrupt-map:
34    maxItems: 16
35
36  interrupt-map-mask:
37    items:
38      - const: 0x1800
39      - const: 0
40      - const: 0
41      - const: 7
42
43required:
44  - compatible
45  - reg
46  - ranges
47  - "#interrupt-cells"
48  - interrupt-map
49  - interrupt-map-mask
50
51examples:
52  - |
53    pci@10001000 {
54      compatible = "arm,versatile-pci";
55      device_type = "pci";
56      reg = <0x10001000 0x1000>,
57            <0x41000000 0x10000>,
58            <0x42000000 0x100000>;
59      bus-range = <0 0xff>;
60      #address-cells = <3>;
61      #size-cells = <2>;
62      #interrupt-cells = <1>;
63
64      ranges =
65          <0x01000000 0 0x00000000 0x43000000 0 0x00010000>,  /* downstream I/O */
66          <0x02000000 0 0x50000000 0x50000000 0 0x10000000>,  /* non-prefetchable memory */
67          <0x42000000 0 0x60000000 0x60000000 0 0x10000000>;  /* prefetchable memory */
68
69      interrupt-map-mask = <0x1800 0 0 7>;
70      interrupt-map = <0x1800 0 0 1 &sic 28>,
71          <0x1800 0 0 2 &sic 29>,
72          <0x1800 0 0 3 &sic 30>,
73          <0x1800 0 0 4 &sic 27>,
74
75          <0x1000 0 0 1 &sic 27>,
76          <0x1000 0 0 2 &sic 28>,
77          <0x1000 0 0 3 &sic 29>,
78          <0x1000 0 0 4 &sic 30>,
79
80          <0x0800 0 0 1 &sic 30>,
81          <0x0800 0 0 2 &sic 27>,
82          <0x0800 0 0 3 &sic 28>,
83          <0x0800 0 0 4 &sic 29>,
84
85          <0x0000 0 0 1 &sic 29>,
86          <0x0000 0 0 2 &sic 30>,
87          <0x0000 0 0 3 &sic 27>,
88          <0x0000 0 0 4 &sic 28>;
89    };
90
91
92...
93