117c1b163SNobuhiro Iwamatsu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 217c1b163SNobuhiro Iwamatsu%YAML 1.2 317c1b163SNobuhiro Iwamatsu--- 417c1b163SNobuhiro Iwamatsu$id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml# 517c1b163SNobuhiro Iwamatsu$schema: http://devicetree.org/meta-schemas/core.yaml# 617c1b163SNobuhiro Iwamatsu 7dd3cb467SAndrew Lunntitle: Toshiba Visconti5 SoC PCIe Host Controller 817c1b163SNobuhiro Iwamatsu 917c1b163SNobuhiro Iwamatsumaintainers: 1017c1b163SNobuhiro Iwamatsu - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 1117c1b163SNobuhiro Iwamatsu 1217c1b163SNobuhiro Iwamatsudescription: 1317c1b163SNobuhiro Iwamatsu Toshiba Visconti5 SoC PCIe host controller is based on the Synopsys DesignWare PCIe IP. 1417c1b163SNobuhiro Iwamatsu 1517c1b163SNobuhiro IwamatsuallOf: 1617c1b163SNobuhiro Iwamatsu - $ref: /schemas/pci/snps,dw-pcie.yaml# 1717c1b163SNobuhiro Iwamatsu 1817c1b163SNobuhiro Iwamatsuproperties: 1917c1b163SNobuhiro Iwamatsu compatible: 2017c1b163SNobuhiro Iwamatsu const: toshiba,visconti-pcie 2117c1b163SNobuhiro Iwamatsu 2217c1b163SNobuhiro Iwamatsu reg: 2317c1b163SNobuhiro Iwamatsu items: 2417c1b163SNobuhiro Iwamatsu - description: Data Bus Interface (DBI) registers. 2517c1b163SNobuhiro Iwamatsu - description: PCIe configuration space region. 2617c1b163SNobuhiro Iwamatsu - description: Visconti specific additional registers. 2717c1b163SNobuhiro Iwamatsu - description: Visconti specific SMU registers 2817c1b163SNobuhiro Iwamatsu - description: Visconti specific memory protection unit registers (MPU) 2917c1b163SNobuhiro Iwamatsu 3017c1b163SNobuhiro Iwamatsu reg-names: 3117c1b163SNobuhiro Iwamatsu items: 3217c1b163SNobuhiro Iwamatsu - const: dbi 3317c1b163SNobuhiro Iwamatsu - const: config 3417c1b163SNobuhiro Iwamatsu - const: ulreg 3517c1b163SNobuhiro Iwamatsu - const: smu 3617c1b163SNobuhiro Iwamatsu - const: mpu 3717c1b163SNobuhiro Iwamatsu 3817c1b163SNobuhiro Iwamatsu interrupts: 39*4cf4b9b7SSerge Semin maxItems: 2 4017c1b163SNobuhiro Iwamatsu 4117c1b163SNobuhiro Iwamatsu clocks: 4217c1b163SNobuhiro Iwamatsu items: 4317c1b163SNobuhiro Iwamatsu - description: PCIe reference clock 4417c1b163SNobuhiro Iwamatsu - description: PCIe system clock 4517c1b163SNobuhiro Iwamatsu - description: Auxiliary clock 4617c1b163SNobuhiro Iwamatsu 4717c1b163SNobuhiro Iwamatsu clock-names: 4817c1b163SNobuhiro Iwamatsu items: 4917c1b163SNobuhiro Iwamatsu - const: ref 5017c1b163SNobuhiro Iwamatsu - const: core 5117c1b163SNobuhiro Iwamatsu - const: aux 5217c1b163SNobuhiro Iwamatsu 5317c1b163SNobuhiro Iwamatsu num-lanes: 5417c1b163SNobuhiro Iwamatsu const: 2 5517c1b163SNobuhiro Iwamatsu 5617c1b163SNobuhiro Iwamatsurequired: 5717c1b163SNobuhiro Iwamatsu - reg 5817c1b163SNobuhiro Iwamatsu - reg-names 5917c1b163SNobuhiro Iwamatsu - interrupts 6017c1b163SNobuhiro Iwamatsu - "#interrupt-cells" 6117c1b163SNobuhiro Iwamatsu - interrupt-map 6217c1b163SNobuhiro Iwamatsu - interrupt-map-mask 6317c1b163SNobuhiro Iwamatsu - num-lanes 6417c1b163SNobuhiro Iwamatsu - clocks 6517c1b163SNobuhiro Iwamatsu - clock-names 6617c1b163SNobuhiro Iwamatsu - max-link-speed 6717c1b163SNobuhiro Iwamatsu 6817c1b163SNobuhiro IwamatsuunevaluatedProperties: false 6917c1b163SNobuhiro Iwamatsu 7017c1b163SNobuhiro Iwamatsuexamples: 7117c1b163SNobuhiro Iwamatsu - | 7217c1b163SNobuhiro Iwamatsu #include <dt-bindings/interrupt-controller/irq.h> 7317c1b163SNobuhiro Iwamatsu #include <dt-bindings/interrupt-controller/arm-gic.h> 7417c1b163SNobuhiro Iwamatsu 7517c1b163SNobuhiro Iwamatsu soc { 7617c1b163SNobuhiro Iwamatsu #address-cells = <2>; 7717c1b163SNobuhiro Iwamatsu #size-cells = <2>; 7817c1b163SNobuhiro Iwamatsu 7917c1b163SNobuhiro Iwamatsu pcie: pcie@28400000 { 8017c1b163SNobuhiro Iwamatsu compatible = "toshiba,visconti-pcie"; 8117c1b163SNobuhiro Iwamatsu reg = <0x0 0x28400000 0x0 0x00400000>, 8217c1b163SNobuhiro Iwamatsu <0x0 0x70000000 0x0 0x10000000>, 8317c1b163SNobuhiro Iwamatsu <0x0 0x28050000 0x0 0x00010000>, 8417c1b163SNobuhiro Iwamatsu <0x0 0x24200000 0x0 0x00002000>, 8517c1b163SNobuhiro Iwamatsu <0x0 0x24162000 0x0 0x00001000>; 8617c1b163SNobuhiro Iwamatsu reg-names = "dbi", "config", "ulreg", "smu", "mpu"; 8717c1b163SNobuhiro Iwamatsu device_type = "pci"; 8817c1b163SNobuhiro Iwamatsu bus-range = <0x00 0xff>; 8917c1b163SNobuhiro Iwamatsu num-lanes = <2>; 9017c1b163SNobuhiro Iwamatsu num-viewport = <8>; 9117c1b163SNobuhiro Iwamatsu 9217c1b163SNobuhiro Iwamatsu #address-cells = <3>; 9317c1b163SNobuhiro Iwamatsu #size-cells = <2>; 9417c1b163SNobuhiro Iwamatsu #interrupt-cells = <1>; 9517c1b163SNobuhiro Iwamatsu ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000>, 9617c1b163SNobuhiro Iwamatsu <0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>; 97*4cf4b9b7SSerge Semin interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 98*4cf4b9b7SSerge Semin <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 99*4cf4b9b7SSerge Semin interrupt-names = "msi", "intr"; 10017c1b163SNobuhiro Iwamatsu interrupt-map-mask = <0 0 0 7>; 10117c1b163SNobuhiro Iwamatsu interrupt-map = 10217c1b163SNobuhiro Iwamatsu <0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 10317c1b163SNobuhiro Iwamatsu 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 10417c1b163SNobuhiro Iwamatsu 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 10517c1b163SNobuhiro Iwamatsu 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 10617c1b163SNobuhiro Iwamatsu clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>; 10717c1b163SNobuhiro Iwamatsu clock-names = "ref", "core", "aux"; 10817c1b163SNobuhiro Iwamatsu max-link-speed = <2>; 10917c1b163SNobuhiro Iwamatsu }; 11017c1b163SNobuhiro Iwamatsu }; 11117c1b163SNobuhiro Iwamatsu... 112