1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: TI J721E PCI Host (PCIe Wrapper) 9 10maintainers: 11 - Kishon Vijay Abraham I <kishon@ti.com> 12 13allOf: 14 - $ref: "cdns-pcie-host.yaml#" 15 16properties: 17 compatible: 18 enum: 19 - ti,j721e-pcie-host 20 21 reg: 22 maxItems: 4 23 24 reg-names: 25 items: 26 - const: intd_cfg 27 - const: user_cfg 28 - const: reg 29 - const: cfg 30 31 ti,syscon-pcie-ctrl: 32 description: Phandle to the SYSCON entry required for configuring PCIe mode 33 and link speed. 34 $ref: /schemas/types.yaml#/definitions/phandle 35 36 power-domains: 37 maxItems: 1 38 39 clocks: 40 maxItems: 1 41 description: clock-specifier to represent input to the PCIe 42 43 clock-names: 44 items: 45 - const: fck 46 47 vendor-id: 48 const: 0x104c 49 50 device-id: 51 const: 0xb00d 52 53 msi-map: true 54 55required: 56 - compatible 57 - reg 58 - reg-names 59 - ti,syscon-pcie-ctrl 60 - max-link-speed 61 - num-lanes 62 - power-domains 63 - clocks 64 - clock-names 65 - vendor-id 66 - device-id 67 - msi-map 68 - dma-coherent 69 - dma-ranges 70 - ranges 71 - reset-gpios 72 - phys 73 - phy-names 74 75unevaluatedProperties: false 76 77examples: 78 - | 79 #include <dt-bindings/soc/ti,sci_pm_domain.h> 80 #include <dt-bindings/gpio/gpio.h> 81 82 bus { 83 #address-cells = <2>; 84 #size-cells = <2>; 85 86 pcie0_rc: pcie@2900000 { 87 compatible = "ti,j721e-pcie-host"; 88 reg = <0x00 0x02900000 0x00 0x1000>, 89 <0x00 0x02907000 0x00 0x400>, 90 <0x00 0x0d000000 0x00 0x00800000>, 91 <0x00 0x10000000 0x00 0x00001000>; 92 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 93 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 94 max-link-speed = <3>; 95 num-lanes = <2>; 96 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 97 clocks = <&k3_clks 239 1>; 98 clock-names = "fck"; 99 device_type = "pci"; 100 #address-cells = <3>; 101 #size-cells = <2>; 102 bus-range = <0x0 0xf>; 103 vendor-id = <0x104c>; 104 device-id = <0xb00d>; 105 msi-map = <0x0 &gic_its 0x0 0x10000>; 106 dma-coherent; 107 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 108 phys = <&serdes0_pcie_link>; 109 phy-names = "pcie-phy"; 110 ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, 111 <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; 112 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; 113 }; 114 }; 115