1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI J721E PCI EP (PCIe Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13allOf:
14  - $ref: "cdns-pcie-ep.yaml#"
15
16properties:
17  compatible:
18    oneOf:
19      - description: PCIe EP controller in J7200
20        items:
21          - const: ti,j7200-pcie-ep
22          - const: ti,j721e-pcie-ep
23      - description: PCIe EP controller in J721E
24        items:
25          - const: ti,j721e-pcie-ep
26
27  reg:
28    maxItems: 4
29
30  reg-names:
31    items:
32      - const: intd_cfg
33      - const: user_cfg
34      - const: reg
35      - const: mem
36
37  ti,syscon-pcie-ctrl:
38    $ref: /schemas/types.yaml#/definitions/phandle-array
39    items:
40      - items:
41          - description: Phandle to the SYSCON entry
42          - description: pcie_ctrl register offset within SYSCON
43    description: Specifier for configuring PCIe mode and link speed.
44
45  power-domains:
46    maxItems: 1
47
48  clocks:
49    maxItems: 1
50    description: clock-specifier to represent input to the PCIe
51
52  clock-names:
53    items:
54      - const: fck
55
56  dma-coherent:
57    description: Indicates that the PCIe IP block can ensure the coherency
58
59required:
60  - compatible
61  - reg
62  - reg-names
63  - ti,syscon-pcie-ctrl
64  - max-link-speed
65  - num-lanes
66  - power-domains
67  - clocks
68  - clock-names
69  - dma-coherent
70  - max-functions
71  - phys
72  - phy-names
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/soc/ti,sci_pm_domain.h>
79
80    bus {
81        #address-cells = <2>;
82        #size-cells = <2>;
83
84        pcie0_ep: pcie-ep@d000000 {
85           compatible = "ti,j721e-pcie-ep";
86           reg = <0x00 0x02900000 0x00 0x1000>,
87                 <0x00 0x02907000 0x00 0x400>,
88                 <0x00 0x0d000000 0x00 0x00800000>,
89                 <0x00 0x10000000 0x00 0x08000000>;
90           reg-names = "intd_cfg", "user_cfg", "reg", "mem";
91           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
92           max-link-speed = <3>;
93           num-lanes = <2>;
94           power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
95           clocks = <&k3_clks 239 1>;
96           clock-names = "fck";
97           max-functions = /bits/ 8 <6>;
98           dma-coherent;
99           phys = <&serdes0_pcie_link>;
100           phy-names = "pcie-phy";
101       };
102    };
103