1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 3%YAML 1.2 4--- 5$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#" 6$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7 8title: TI J721E PCI EP (PCIe Wrapper) 9 10maintainers: 11 - Kishon Vijay Abraham I <kishon@ti.com> 12 13allOf: 14 - $ref: "cdns-pcie-ep.yaml#" 15 16properties: 17 compatible: 18 enum: 19 - ti,j721e-pcie-ep 20 21 reg: 22 maxItems: 4 23 24 reg-names: 25 items: 26 - const: intd_cfg 27 - const: user_cfg 28 - const: reg 29 - const: mem 30 31 ti,syscon-pcie-ctrl: 32 description: Phandle to the SYSCON entry required for configuring PCIe mode 33 and link speed. 34 $ref: /schemas/types.yaml#/definitions/phandle 35 36 power-domains: 37 maxItems: 1 38 39 clocks: 40 maxItems: 1 41 description: clock-specifier to represent input to the PCIe 42 43 clock-names: 44 items: 45 - const: fck 46 47 dma-coherent: 48 description: Indicates that the PCIe IP block can ensure the coherency 49 50required: 51 - compatible 52 - reg 53 - reg-names 54 - ti,syscon-pcie-ctrl 55 - max-link-speed 56 - num-lanes 57 - power-domains 58 - clocks 59 - clock-names 60 - dma-coherent 61 - max-functions 62 - phys 63 - phy-names 64 65unevaluatedProperties: false 66 67examples: 68 - | 69 #include <dt-bindings/soc/ti,sci_pm_domain.h> 70 71 bus { 72 #address-cells = <2>; 73 #size-cells = <2>; 74 75 pcie0_ep: pcie-ep@d000000 { 76 compatible = "ti,j721e-pcie-ep"; 77 reg = <0x00 0x02900000 0x00 0x1000>, 78 <0x00 0x02907000 0x00 0x400>, 79 <0x00 0x0d000000 0x00 0x00800000>, 80 <0x00 0x10000000 0x00 0x08000000>; 81 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 82 ti,syscon-pcie-ctrl = <&pcie0_ctrl>; 83 max-link-speed = <3>; 84 num-lanes = <2>; 85 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>; 86 clocks = <&k3_clks 239 1>; 87 clock-names = "fck"; 88 max-functions = /bits/ 8 <6>; 89 dma-coherent; 90 phys = <&serdes0_pcie_link>; 91 phy-names = "pcie-phy"; 92 }; 93 }; 94