1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI J721E PCI EP (PCIe Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13allOf:
14  - $ref: "cdns-pcie-ep.yaml#"
15
16properties:
17  compatible:
18    enum:
19      - ti,j721e-pcie-ep
20
21  reg:
22    maxItems: 4
23
24  reg-names:
25    items:
26      - const: intd_cfg
27      - const: user_cfg
28      - const: reg
29      - const: mem
30
31  ti,syscon-pcie-ctrl:
32    description: Phandle to the SYSCON entry required for configuring PCIe mode
33                 and link speed.
34    allOf:
35      - $ref: /schemas/types.yaml#/definitions/phandle
36
37  power-domains:
38    maxItems: 1
39
40  clocks:
41    maxItems: 1
42    description: clock-specifier to represent input to the PCIe
43
44  clock-names:
45    items:
46      - const: fck
47
48  dma-coherent:
49    description: Indicates that the PCIe IP block can ensure the coherency
50
51required:
52  - compatible
53  - reg
54  - reg-names
55  - ti,syscon-pcie-ctrl
56  - max-link-speed
57  - num-lanes
58  - power-domains
59  - clocks
60  - clock-names
61  - cdns,max-outbound-regions
62  - dma-coherent
63  - max-functions
64  - phys
65  - phy-names
66
67examples:
68  - |
69    #include <dt-bindings/soc/ti,sci_pm_domain.h>
70
71    bus {
72        #address-cells = <2>;
73        #size-cells = <2>;
74
75        pcie0_ep: pcie-ep@d000000 {
76           compatible = "ti,j721e-pcie-ep";
77           reg = <0x00 0x02900000 0x00 0x1000>,
78                 <0x00 0x02907000 0x00 0x400>,
79                 <0x00 0x0d000000 0x00 0x00800000>,
80                 <0x00 0x10000000 0x00 0x08000000>;
81           reg-names = "intd_cfg", "user_cfg", "reg", "mem";
82           ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
83           max-link-speed = <3>;
84           num-lanes = <2>;
85           power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
86           clocks = <&k3_clks 239 1>;
87           clock-names = "fck";
88           cdns,max-outbound-regions = <16>;
89           max-functions = /bits/ 8 <6>;
90           dma-coherent;
91           phys = <&serdes0_pcie_link>;
92           phy-names = "pcie-phy";
93       };
94    };
95