1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Socionext UniPhier PCIe host controller
8
9description: |
10  UniPhier PCIe host controller is based on the Synopsys DesignWare
11  PCI core. It shares common features with the PCIe DesignWare core and
12  inherits common properties defined in
13  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
14
15maintainers:
16  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17
18allOf:
19  - $ref: /schemas/pci/snps,dw-pcie.yaml#
20
21properties:
22  compatible:
23    enum:
24      - socionext,uniphier-pcie
25
26  reg:
27    minItems: 3
28    maxItems: 4
29
30  reg-names:
31    minItems: 3
32    items:
33      - const: dbi
34      - const: link
35      - const: config
36      - const: atu
37
38  clocks:
39    maxItems: 1
40
41  resets:
42    maxItems: 1
43
44  num-viewport: true
45
46  num-lanes: true
47
48  phys:
49    maxItems: 1
50
51  phy-names:
52    const: pcie-phy
53
54required:
55  - compatible
56  - reg
57  - reg-names
58  - clocks
59  - resets
60
61unevaluatedProperties: false
62
63examples:
64  - |
65    pcie: pcie@66000000 {
66        compatible = "socionext,uniphier-pcie";
67        reg-names = "dbi", "link", "config";
68        reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
69        #address-cells = <3>;
70        #size-cells = <2>;
71        clocks = <&sys_clk 24>;
72        resets = <&sys_rst 24>;
73        num-lanes = <1>;
74        num-viewport = <1>;
75        bus-range = <0x0 0xff>;
76        device_type = "pci";
77        ranges = <0x81000000 0 0x00000000  0x2ffe0000  0 0x00010000>,
78                 <0x82000000 0 0x00000000  0x20000000  0 0x0ffe0000>;
79        phy-names = "pcie-phy";
80        phys = <&pcie_phy>;
81        #interrupt-cells = <1>;
82        interrupt-names = "dma", "msi";
83        interrupts = <0 224 4>, <0 225 4>;
84        interrupt-map-mask = <0 0 0  7>;
85        interrupt-map = <0 0 0  1  &pcie_intc 0>,
86                        <0 0 0  2  &pcie_intc 1>,
87                        <0 0 0  3  &pcie_intc 2>,
88                        <0 0 0  4  &pcie_intc 3>;
89
90        pcie_intc: legacy-interrupt-controller {
91            interrupt-controller;
92            #interrupt-cells = <1>;
93            interrupt-parent = <&gic>;
94            interrupts = <0 226 4>;
95        };
96    };
97