1*d9a64c5eSKunihiko Hayashi# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*d9a64c5eSKunihiko Hayashi%YAML 1.2
3*d9a64c5eSKunihiko Hayashi---
4*d9a64c5eSKunihiko Hayashi$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5*d9a64c5eSKunihiko Hayashi$schema: http://devicetree.org/meta-schemas/core.yaml#
6*d9a64c5eSKunihiko Hayashi
7*d9a64c5eSKunihiko Hayashititle: Socionext UniPhier PCIe host controller
8*d9a64c5eSKunihiko Hayashi
9*d9a64c5eSKunihiko Hayashidescription: |
10*d9a64c5eSKunihiko Hayashi  UniPhier PCIe host controller is based on the Synopsys DesignWare
11*d9a64c5eSKunihiko Hayashi  PCI core. It shares common features with the PCIe DesignWare core and
12*d9a64c5eSKunihiko Hayashi  inherits common properties defined in
13*d9a64c5eSKunihiko Hayashi  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
14*d9a64c5eSKunihiko Hayashi
15*d9a64c5eSKunihiko Hayashimaintainers:
16*d9a64c5eSKunihiko Hayashi  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17*d9a64c5eSKunihiko Hayashi
18*d9a64c5eSKunihiko HayashiallOf:
19*d9a64c5eSKunihiko Hayashi  - $ref: /schemas/pci/snps,dw-pcie.yaml#
20*d9a64c5eSKunihiko Hayashi
21*d9a64c5eSKunihiko Hayashiproperties:
22*d9a64c5eSKunihiko Hayashi  compatible:
23*d9a64c5eSKunihiko Hayashi    enum:
24*d9a64c5eSKunihiko Hayashi      - socionext,uniphier-pcie
25*d9a64c5eSKunihiko Hayashi
26*d9a64c5eSKunihiko Hayashi  reg:
27*d9a64c5eSKunihiko Hayashi    minItems: 3
28*d9a64c5eSKunihiko Hayashi    maxItems: 4
29*d9a64c5eSKunihiko Hayashi
30*d9a64c5eSKunihiko Hayashi  reg-names:
31*d9a64c5eSKunihiko Hayashi    minItems: 3
32*d9a64c5eSKunihiko Hayashi    items:
33*d9a64c5eSKunihiko Hayashi      - const: dbi
34*d9a64c5eSKunihiko Hayashi      - const: link
35*d9a64c5eSKunihiko Hayashi      - const: config
36*d9a64c5eSKunihiko Hayashi      - const: atu
37*d9a64c5eSKunihiko Hayashi
38*d9a64c5eSKunihiko Hayashi  clocks:
39*d9a64c5eSKunihiko Hayashi    maxItems: 1
40*d9a64c5eSKunihiko Hayashi
41*d9a64c5eSKunihiko Hayashi  resets:
42*d9a64c5eSKunihiko Hayashi    maxItems: 1
43*d9a64c5eSKunihiko Hayashi
44*d9a64c5eSKunihiko Hayashi  num-viewport: true
45*d9a64c5eSKunihiko Hayashi
46*d9a64c5eSKunihiko Hayashi  num-lanes: true
47*d9a64c5eSKunihiko Hayashi
48*d9a64c5eSKunihiko Hayashi  phys:
49*d9a64c5eSKunihiko Hayashi    maxItems: 1
50*d9a64c5eSKunihiko Hayashi
51*d9a64c5eSKunihiko Hayashi  phy-names:
52*d9a64c5eSKunihiko Hayashi    const: pcie-phy
53*d9a64c5eSKunihiko Hayashi
54*d9a64c5eSKunihiko Hayashirequired:
55*d9a64c5eSKunihiko Hayashi  - compatible
56*d9a64c5eSKunihiko Hayashi  - reg
57*d9a64c5eSKunihiko Hayashi  - reg-names
58*d9a64c5eSKunihiko Hayashi  - clocks
59*d9a64c5eSKunihiko Hayashi  - resets
60*d9a64c5eSKunihiko Hayashi
61*d9a64c5eSKunihiko HayashiunevaluatedProperties: false
62*d9a64c5eSKunihiko Hayashi
63*d9a64c5eSKunihiko Hayashiexamples:
64*d9a64c5eSKunihiko Hayashi  - |
65*d9a64c5eSKunihiko Hayashi    pcie: pcie@66000000 {
66*d9a64c5eSKunihiko Hayashi        compatible = "socionext,uniphier-pcie";
67*d9a64c5eSKunihiko Hayashi        reg-names = "dbi", "link", "config";
68*d9a64c5eSKunihiko Hayashi        reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
69*d9a64c5eSKunihiko Hayashi        #address-cells = <3>;
70*d9a64c5eSKunihiko Hayashi        #size-cells = <2>;
71*d9a64c5eSKunihiko Hayashi        clocks = <&sys_clk 24>;
72*d9a64c5eSKunihiko Hayashi        resets = <&sys_rst 24>;
73*d9a64c5eSKunihiko Hayashi        num-lanes = <1>;
74*d9a64c5eSKunihiko Hayashi        num-viewport = <1>;
75*d9a64c5eSKunihiko Hayashi        bus-range = <0x0 0xff>;
76*d9a64c5eSKunihiko Hayashi        device_type = "pci";
77*d9a64c5eSKunihiko Hayashi        ranges = <0x81000000 0 0x00000000  0x2ffe0000  0 0x00010000>,
78*d9a64c5eSKunihiko Hayashi                 <0x82000000 0 0x00000000  0x20000000  0 0x0ffe0000>;
79*d9a64c5eSKunihiko Hayashi        phy-names = "pcie-phy";
80*d9a64c5eSKunihiko Hayashi        phys = <&pcie_phy>;
81*d9a64c5eSKunihiko Hayashi        #interrupt-cells = <1>;
82*d9a64c5eSKunihiko Hayashi        interrupt-names = "dma", "msi";
83*d9a64c5eSKunihiko Hayashi        interrupts = <0 224 4>, <0 225 4>;
84*d9a64c5eSKunihiko Hayashi        interrupt-map-mask = <0 0 0  7>;
85*d9a64c5eSKunihiko Hayashi        interrupt-map = <0 0 0  1  &pcie_intc 0>,
86*d9a64c5eSKunihiko Hayashi                        <0 0 0  2  &pcie_intc 1>,
87*d9a64c5eSKunihiko Hayashi                        <0 0 0  3  &pcie_intc 2>,
88*d9a64c5eSKunihiko Hayashi                        <0 0 0  4  &pcie_intc 3>;
89*d9a64c5eSKunihiko Hayashi
90*d9a64c5eSKunihiko Hayashi        pcie_intc: legacy-interrupt-controller {
91*d9a64c5eSKunihiko Hayashi            interrupt-controller;
92*d9a64c5eSKunihiko Hayashi            #interrupt-cells = <1>;
93*d9a64c5eSKunihiko Hayashi            interrupt-parent = <&gic>;
94*d9a64c5eSKunihiko Hayashi            interrupts = <0 226 4>;
95*d9a64c5eSKunihiko Hayashi        };
96*d9a64c5eSKunihiko Hayashi    };
97